Abstract: An efficient memory controller. The controller includes a first mechanism for associating one or more input command sequences with one or more corresponding values. A second mechanism selectively sequences one of the one or more command sequences to a memory in response to a signal. A third mechanism compares each of the one or more values to a state of the second mechanism and provides the signal in response thereto. In a specific embodiment, the one or more corresponding values are execution time code values, and the second mechanism includes a sequencer state machine that provides the state of the second mechanism as a sequencer time code. In the specific embodiment, a compare module compares the sequencer time code to a time code associated with a next available command sequence and execution time code pair and provides the signal in response thereto.

Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.

Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26). The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.

Abstract: An efficient memory controller. The controller includes a first mechanism for associating one or more input command sequences with one or more corresponding values. A second mechanism selectively sequences one of the one or more command sequences to a memory in response to a signal. A third mechanism compares each of the one or more values to a state of the second mechanism and provides the signal in response thereto. In a specific embodiment, the one or more corresponding values are execution time code values, and the second mechanism includes a sequencer state machine that provides the state of the second mechanism as a sequencer time code. In the specific embodiment, a compare module compares the sequencer time code to a time code associated with a next available command sequence and execution time code pair and provides the signal in response thereto.

Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26). The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.