Abstract: A device (2) for training and stimulation of dogs or children, which device (2) comprises a number of elements (6, 6?, 8, 8?, 74, 76, 78, 80, 88, 88?, 90, 90?) configured to be locked and thereby fix and at least partly hide a number of tidbits (4, 4?, 4?, 4?), wherein the device (2) has activation members (12, 12?, 12?, 12??, 14, 16, 26) for opening/detachment of the elements (6, 6?, 8, 8?, 74, 76, 78, 80, 88, 88?, 90, 90?). The elements (6, 6?, 8, 8?, 74, 76, 78, 80, 88, 88?, 90, 90?) prevent one or more of the other elements (6, 6?, 8, 8?, 74, 76, 78, 80, 88, 88?, 90, 90?) from being opened/detached in such a manner that a first element (8?) is required to be opened/detached in order to open/detach another element (8).

Abstract: A system and method for detecting and handling errors in a computer system are disclosed. The invention is configurable to permit selecting of timelength or time out values, assigned interrupts to be generated and error recover procedures so that failures of system events can be promptly detected and recovered from. The watchdog timer is started with a timelength or time out value and generates an interrupt (i.e., is triggered) if the period of time set as the timelength passes without receiving a reset. The watchdog timer interface interacts and controls the hardware based timer to obtain this watchdog timer functionality. The hardware based timer is generally a high precision timer that exists in hardware architecture for a computer system and is usable by system software. The watchdog timer interface controls and sets various parameters and/or registers of the hardware based timer in order to provide the desired functionality of a watchdog timer.

Abstract: A system and method for detecting and handling errors in a computer system are disclosed. The invention is configurable to permit selecting of timelength or time out values, assigned interrupts to be generated and error recover procedures so that failures of system events can be promptly detected and recovered from. The watchdog timer is started with a timelength or time out value and generates an interrupt (i.e., is triggered) if the period of time set as the timelength passes without receiving a reset. The watchdog timer interface interacts and controls the hardware based timer to obtain this watchdog timer functionality. The hardware based timer is generally a high precision timer that exists in hardware architecture for a computer system and is usable by system software. The watchdog timer interface controls and sets various parameters and/or registers of the hardware based timer in order to provide the desired functionality of a watchdog timer.

Abstract: Fan horsepower requirements and the size of power train heat exchangers may be reduced in a vehicular cooling system that includes an inlet (14) for the receipt of ambient air and first and second heat exchangers (28), (40) in proximity to the inlet (14) to receive ambient air therefrom and which are respectively adapted to receive first and second heat exchanger fluids by the ambient air. The first and second heat exchangers (28), (40) are in side by side, substantially non superimposed relation to define first and second air flow paths (52, 54) extending in fluid flow parallel to a respective one of the heat exchangers (28), (40) from the inlet (14) to points (50), (52), (54) of discharge. A fan (44) flows air from the inlet (14) through the flow paths (52, 54) and a shutter (56) is located in one of the flow paths (54) and is movable between first and second positions respectively restricting air flow and allowing relatively unrestricted air flow.

Abstract: A data communication system having a master unit, an interface, and one or more remote units. The master unit includes a programmable controller having a data processor, memory storage for storing programs and command and data bytes, and address and data buses. The interface is connected to the master unit via the address and data buses, and includes a memory connected to the data bus for temporarily storing command and output data bytes from the master unit pending transmittal thereof to the remote units and for storing input data bytes from the remote units pending transfer thereof to the master unit. A first communication path, along which command and data bytes from the interface memory are transmitted to the remote units, couples the interface with the remote units. A second communication path, along which input data bytes from the remote units to the interface memory are transmitted, couples the remote units with the interface.