Patents by Inventor Frank Niklaus

Frank Niklaus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200378902
    Abstract: Disclosed is a method of making a crack structure on a substrate, the crack structure being usable as a tunnelling junction structure in a nanogap device, including the controlled fracture or release of a patterned layer under built-in stress, thereby forming elements separated by nanogaps or crack-junctions. The width of the crack-defined nanogap is controlled by locally release-etching the film at a notched bridge patterned in the film. The built-in stress contributes to forming the crack and defining of the width of the crack-defined nanogap. Further, by design of the length of the bridge in a range between sub-??? to >25 ???, the separation between the elements, defined by the width of the crack-defined nanogaps, can be controlled for each individual crack structure from <2 nm to >100 nm. The nanogaps can be used for tunneling devices in combination with nanopores for DNA, RNA or peptides sequencing.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Inventors: Valentin DUBOIS, Frank NIKLAUS, Göran STEMME
  • Patent number: 10782249
    Abstract: Disclosed is a method of making a crack structure on a substrate, the crack structure being usable as a tunneling junction structure in a nanogap device, including the controlled fracture or release of a patterned layer under built-in stress, thereby forming elements separated by nanogaps or crack-junctions. The width of the crack-defined nanogap is controlled by locally release-etching the film at a notched bridge patterned in the film. The built-in stress contributes to forming the crack and defining of the width of the crack-defined nanogap. Further, by design of the length of the bridge in a range between sub-??? to >25???, the separation between the elements, defined by the width of the crack-defined nanogaps, can be controlled for each individual crack structure from <2 nm to >100 nm. The nanogaps can be used for tunneling devices in combination with nanopores for DNA, RNA or peptides sequencing.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 22, 2020
    Assignee: ZEDNA AB
    Inventors: Valentin Dubois, Frank Niklaus, Göran Stemme
  • Publication number: 20180372653
    Abstract: Disclosed is a method of making a crack structure on a substrate, the crack structure being usable as a tunneling junction structure in a nanogap device, including the controlled fracture or release of a patterned layer under built-in stress, thereby forming elements separated by nanogaps or crack-junctions. The width of the crack-defined nanogap is controlled by locally release-etching the film at a notched bridge patterned in the film. The built-in stress contributes to forming the crack and defining of the width of the crack-defined nanogap. Further, by design of the length of the bridge in a range between sub-??? to >25???, the separation between the elements, defined by the width of the crack-defined nanogaps, can be controlled for each individual crack structure from <2 nm to >100 nm. The nanogaps can be used for tunneling devices in combination with nanopores for DNA, RNA or peptides sequencing.
    Type: Application
    Filed: December 14, 2016
    Publication date: December 27, 2018
    Inventors: Valentin DUBOIS, Frank NIKLAUS, Göran STEMME
  • Patent number: 9054162
    Abstract: A method is disclosed for forming conductive vias in a substrate by filling preformed via holes, preferably through via holes, with conductive material. The method includes providing a plurality of preformed objects at least partly including ferromagnetic material on a surface of the substrate; providing a magnetic source on an opposite side of the substrate with respect to the plurality of preformed objects, thereby at least partly aligning at least a portion of the preformed objects with a magnetic field associated with the magnetic source; and moving the magnetic source relative the substrate, or vice versa, thereby moving the at least portion of the preformed objects into at least a portion of the via holes.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: June 9, 2015
    Inventors: Andreas Fischer, Göran Stemme, Frank Niklaus
  • Patent number: 9054224
    Abstract: The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: June 9, 2015
    Assignee: SENSEAIR AB
    Inventors: Stefan Braun, Frank Niklaus, Andreas Fischer, Henrik Gradin
  • Patent number: 9027239
    Abstract: A method for at least partially inserting a plug into a hole, said method comprising the steps of a) providing a at least one substrate with at least one hole wherein said at least one hole has a largest dimension of from 1 ?m to 300 ?m, b) providing a piece of material, wherein said piece of material has a larger dimension than said at least one hole, c) pressing said piece of material against the hole with a tool so that a plug is formed, wherein at least a part of said piece of material is pressed into said hole, d) removing the tool from the piece of material. There is further disclosed a plugged hole manufactured with the method. One advantage of an embodiment is that an industrially available wire bonding technology can be used to seal various cavities. The existing wire bonding technology makes the plugging fast and cheap.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: May 12, 2015
    Assignee: Aerocrine AB
    Inventors: Andreas Fischer, Göran Stemme, Frank Niklaus, Niklas Roxhed
  • Publication number: 20150090043
    Abstract: Embodiments provide a MEMS including a MEMS device and an detector circuit. The MEMS device includes a membrane, wherein a material of the membrane comprises a band gap and a crystal structure with structural elements (unit cells) connected by covalent bonds in two dimensions only. The detector circuit is configured to determine a deformation of the membrane based on a piezoresistive resistance of the material of the membrane.
    Type: Application
    Filed: September 26, 2014
    Publication date: April 2, 2015
    Inventors: Guenther Ruhl, Max Christian Lemme, Alfons Dehe, Andreas Fischer, Frank Niklaus, Anderson Smith
  • Publication number: 20130292856
    Abstract: The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.
    Type: Application
    Filed: November 22, 2011
    Publication date: November 7, 2013
    Applicant: SENSEAIR AB
    Inventors: Stefan Braun, Frank Niklaus, Andreas Fischer, Henrik Gradin
  • Publication number: 20130285256
    Abstract: A method is disclosed for forming conductive vias in a substrate by filling preformed via holes, preferably through via holes, with conductive material. The method includes providing a plurality of preformed objects at least partly including ferromagnetic material on a surface of the substrate; providing a magnetic source on an opposite side of the substrate with respect to the plurality of preformed objects, thereby at least partly aligning at least a portion of the preformed objects with a magnetic field associated with the magnetic source; and moving the magnetic source relative the substrate, or vice versa, thereby moving the at least portion of the preformed objects into at least a portion of the via holes.
    Type: Application
    Filed: November 21, 2011
    Publication date: October 31, 2013
    Inventors: Andreas Fischer, Göran Stemme, Frank Niklaus
  • Publication number: 20130029480
    Abstract: A method of making a three-dimensional structure in semiconductor material includes providing a substrate (20) is provided having at least a surface including semiconductor material. Selected areas of the surface of the substrate are exposed to a focussed ion beam whereby the ions are implanted in the semiconductor material in the selected areas. Several layers of a material selected from the group consisting of mono-crystalline, poly-crystalline or amorphous semiconductor material, are deposited on the substrate surface and between depositions focussed ion beam is used to expose the surface so as to define a three-dimensional structure. Material not part of the final structure (30) defined by the focussed ion beam is etched away so as to provide a three-dimensional structure on the substrate (20).
    Type: Application
    Filed: April 5, 2011
    Publication date: January 31, 2013
    Inventors: Frank Niklaus, Andreas Fischer
  • Publication number: 20130012078
    Abstract: A method for at least partially inserting a plug into a hole, said method comprising the steps of a) providing a at least one substrate with at least one hole wherein said at least one hole has a largest dimension of from 1 ?m to 300 ?m, b) providing a piece of material, wherein said piece of material has a larger dimension than said at least one hole, c) pressing said piece of material against the hole with a tool so that a plug is formed, wherein at least a part of said piece of material is pressed into said hole, d) removing the tool from the piece of material. There is further disclosed a plugged hole manufactured with the method. One advantage of an embodiment is that an industrially available wire bonding technology can be used to seal various cavities. The existing wire bonding technology makes the plugging fast and cheap.
    Type: Application
    Filed: December 17, 2010
    Publication date: January 10, 2013
    Applicant: AEROCRINE AB
    Inventors: Andreas Fischer, Göran Stemme, Frank Niklaus, Niklas Roxhed
  • Patent number: 7067345
    Abstract: A method of combining components to form an integrated device, wherein the components are provided on a first sacrificial wafer, and a second non-sacrificial wafer, respectively. The sacrificial wafer carries a first plurality of components and the non-sacrificial wafer carries a second plurality of components. The wafers are bonded together with an intermediate bonding material. Optionally the sacrificial wafer is thinned to a desired level. The components of the sacrificial wafer are electrically interconnected to the component(s) on the non-sacrificial wafer. Finally, optionally the intermediate bonding material is stripped away.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: June 27, 2006
    Inventors: Edvard Kälvesten, Göran Stemme, Frank Niklaus
  • Patent number: 7054052
    Abstract: A method of combining components to form an integrated device, wherein at least one first component is provided on a first surface of a sacrificial substrate, and at least one second component is provided on a first surface of a non-sacrificial substrate. At least one support structure is formed on at least one of the first surfaces of the sacrificial substrate, and the non-sacrificial substrate, respectively, such that said at least one support structure is extended outwardly from at least one of the first surfaces. The sacrificial substrate carrying the first component, and the non-sacrificial substrate carrying the second component, respectively, are bonded, so that the first and second surfaces will be facing one another with a distance defined by a thickness of the support structure. At least a part of the sacrificial substrate is removed. The first component and second components are interconnected.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: May 30, 2006
    Inventors: Frank Niklaus, Göran Stemme
  • Publication number: 20050052725
    Abstract: A method of combining components to form an integrated device, wherein at least one first component is provided on a first surface of a sacrificial substrate, and at least one second component is provided on a first surface of a non-sacrificial substrate. At least one support structure is formed on at least one of the first surfaces of the sacrificial substrate, and the non-sacrificial substrate, respectively, such that said at least one support structure is extended outwardly from at least one of the first surfaces. The sacrificial substrate carrying the first component, and the non-sacrificial substrate carrying the second component, respectively, are bonded, so that the first and second surfaces will be facing one another with a distance defined by a thickness of the support structure. At least a part of the sacrificial substrate is removed. The first component and second components are interconnected.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 10, 2005
    Inventors: Frank Niklaus, Goran Stemme
  • Publication number: 20030102079
    Abstract: A method of combining components to form an integrated device, wherein the components are provided on a first sacrificial wafer, and a second non-sacrificial wafer, respectively. The sacrificial wafer carries a first plurality of components and the non-sacrificial wafer carries a second plurality of components. The wafers are bonded together with an intermediate bonding material. Optionally the sacrificial wafer is thinned to a desired level. The components of the sacrificial wafer are electrically interconnected to the component(s) on the non-sacrificial wafer. Finally, optionally the intermediate bonding material is stripped away.
    Type: Application
    Filed: January 6, 2003
    Publication date: June 5, 2003
    Inventors: Edvard Kalvesten, Goran Stemme, Frank Niklaus