Abstract: Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep submicron technologies deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage different that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed.

Abstract: An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.

Abstract: In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.

Abstract: In general, in one aspect, the disclosure describes a delay locked loop (DLL) with a regenerative delay line that includes a cascade of delay stages. A first delay stage includes a two-input delay device which receives a 180 degree phase shifted signal as feedback. This feedback signal configures the delay line into a regenerative amplifier, the frequency response of which has peaking or resonance at the input frequency which results in jitter filtering. The amount of regeneration is determined by relative strength of an input signal and the feedback signal. Relative strength is determined by relative size of devices receiving the signals. The resonant frequency (with or without oscillations) of the delay line may automatically be tuned to the incoming clock frequency by the DLL control loop. Each of the other delay stages may include two-input delay devices with the inputs shorted for uniformity.

Abstract: Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed.

Abstract: In general, in one aspect, the disclosure describes a delay line including a cascade of delay stages where each stage delays the phase a defined amount. Each delay stage includes an active voltage control delay element and one or more passive delay elements (e.g., resistive-capacitive (RC) networks). The aggregate amplitude gain roll-off of an active/passive multi pole delay stage delaying the phase a defined amount is less than the amplitude gain roll-off of a single pole delay stage delaying the phase the defined amount. Accordingly jitter amplification of the active/passive multi pole delay stage is less than that of a single pole delay stage. The power consumption of an active/passive multi pole delay stage is less than an all active multi pole delay stage.

Abstract: A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.

Abstract: An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.

Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

Abstract: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.

Abstract: A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock signal through a clock path. A feedback circuit is coupled (i) to the clock path to monitor offset in the clock signal, and (ii) to the clock driver to digitally control the clock driver offset based on the monitored clock signal offset. Other embodiments are disclosed herein.

Abstract: In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.

Abstract: An communication system having an on-chip transmitter circuit connected to a channel via an output connection pad and an on-chip receiver circuit connected to the channel via an input connection pad, wherein the on-chip transmitter circuit includes an equalizing output impedance and the on-chip receiver circuit includes an equalizing input impedance. The equalizing output impedance of the on-chip transmitter circuit is adapted to equalize the pad-capacitance of the output connection pad, whereas the equalizing input impedance of the on-chip receiver circuit is adapted to equalize the pad-capacitance of the input connection pad.

Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.