Abstract: A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed.

Abstract: A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.

Abstract: A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.

Abstract: A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed.

Abstract: A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.

Abstract: A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.

Abstract: A serial communication system includes an integrated circuit having a master serial interface; and a processor having a slave serial interface coupled to the master serial interface through a clock signal line and a data signal line. The slave serial interface is responsive to a read temperature command issued by the master serial interface to return a first temperature value associated with the processor.

Abstract: A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

Abstract: An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.

Abstract: A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.

Abstract: Power management logic maintains memory in a computer system in the self refresh state during a power savings state in which power is removed from the memory controller. A memory control circuit, separate from the power management logic, controls the memory during other operational modes. The power management logic maintains the system memory in the self refresh state by driving memory control signal(s) at appropriate values during the power savings state.

Abstract: The maximum performance state available to a processor in a computer system, in terms of operating frequency and/or voltage, changes according to thermal criteria. When the temperature increases above a predetermined threshold, the maximum performance state available is reduced. Multiple temperature thresholds may be utilized providing for a gradually reduced maximum performance state as temperature increases. When the temperature returns to a lower level, the maximum performance state available is increased. Changing the maximum available performance state according to temperature provides for more gradual reduction in performance as temperature increases, which results in higher average system performance as temperature increases. Thus, a more gradual reduction in performance is provided while still maintaining a high speed rating of the processor in more ideal conditions.

Abstract: An integrated circuit provides for changes to its core clock frequency and its core voltage using software programmable registers on the processor to store voltage ID (VID) values to specify core voltage, which are supplied to a voltage regulator and clock frequency control values, which are supplied to clock generation logic on the integrated circuit to specify core clocks. The integrated circuit generates an internal state in which its core clocks are stopped or slowed and during which core voltage and core frequency are adjusted. The processor also includes a timing mechanism that allows the new voltage and clock frequency to stabilize before resuming core operations. The timing mechanism may include a programmable count to specify the time to allow the new voltage and clock frequency to stabilize.

Abstract: Disclosed herein are a method and apparatus to provide a deterministic power-on voltage in a system having a processor-controlled voltage level. In one embodiment, the system includes a DC/DC converter, a processor, and a selection circuit. The DC/DC converter receives a voltage setting signal or signals from the selection circuit and provides an adjustable power output signal having a voltage indicated by the voltage setting signal. The processor is powered by the adjustable power output signal. When powered, the processor provides a programmable voltage setting signal or signals. The selection circuit receives the programmable voltage setting signal or signals, a hardwired voltage setting signal, and a selection signal or signals, and when the selection signal is in a predetermined condition, the selection circuit provides the programmable voltage setting signal or signals from the processor to the DC/DC converter.

Abstract: The maximum performance state available to a processor in a computer system, in terms of operating frequency and/or voltage, changes according to thermal criteria. When the temperature increases above a predetermined threshold, the maximum performance state available is reduced. Multiple temperature thresholds may be utilized providing for a gradually reduced maximum performance state as temperature increases. When the temperature returns to a lower level, the maximum performance state available is increased. Changing the maximum available performance state according to temperature provides for more gradual reduction in performance as temperature increases, which results in higher average system performance as temperature increases. Thus, a more gradual reduction in performance is provided while still maintaining a high speed rating of the processor in more ideal conditions.

Abstract: Method and apparatus for automatically adjusting the brightness level of an LCD based on the ambient lighting conditions of the environment in which the LCD is being operated are disclosed. In a preferred embodiment, a photodetector located proximate the front of the LCD generates to brightness control circuitry signals indicative of ambient lighting conditions. These signals are correlated to predetermined automatic brightness control values for use in controlling the brightness level of the LCD. Once the ambient light signals have been used automatically to set the brightness level of the LCD, user-selection of a different brightness level, either higher or lower, will override the automatic brightness control setting. In an alternative embodiment, a first photodetector is located proximate the front of the LCD and a second photodetector is located proximate the back of the LCD. In this embodiment, the brighter ambient condition is used to control the brightness level of the LCD.

Abstract: A Peripheral Component Interconnect (PCI) compatible peripheral device for coupling to a PCI bus, the peripheral device comprising a primary function component and a connection portion. The primary function includes a PCI interface for coupling to the PCI bus, and a primary configuration space coupled to the PCI interface and accessible by the PCI bus via the PCI interface. The connection portion is coupled to the primary function component and supports a secondary function component. The primary function component provides PCI bus access via the PCI interface to the secondary function component when the secondary function component is coupled to the connection portion. The primary function component provides PCI bus access via the PCI interface to a secondary configuration space when the secondary function component is coupled to the connection portion.

Abstract: Method and apparatus for automatically adjusting the brightness level of an LCD based on the ambient lighting conditions of the environment in which the LCD is being operated are disclosed. In a preferred embodiment, a photodetector located proximate the front of the LCD generates to brightness control circuitry signals indicative of ambient lighting conditions. These signals are correlated to predetermined automatic brightness control values for use in controlling the brightness level of the LCD. Once the ambient light signals have been used automatically to set the brightness level of the LCD, user-selection of a different brightness level, either higher or lower, will override the automatic brightness control setting. In an alternative embodiment, a first photodetector is located proximate the front of the LCD and a second photodetector is located proximate the back of the LCD. In this embodiment, the brighter ambient condition is used to control the brightness level of the LCD.

Abstract: A system and method for automatically adjusting the volume of an audio system to compensate for variations in ambient noise. The system includes a microphone for monitoring the ambient audio environment which includes output of the audio system plus environmental noise. The system also includes processing circuitry connected to the microphone. The processing circuitry varies the volume of the output of the audio system in proportion to changes in the environmental noise. The processing circuitry comprises the microphone, located to detect the ambient sound in the listening environment, an analog-to-digital converter connected to the output of the microphone, and a digital signal processor connected to the output of the analog-to-digital converter. The output signal of the DSP is an input to the volume control of the audio system.

Abstract: Disclosed are an integrated mouse tray and mouse for a portable computer and method of operation therefor. The computer, including the mouse tray of the present invention, includes: (1) a chassis having a footprint and containing components of the computer, the components including an interface circuit for communicating with a mouse, (2) a mouse electrically coupled to the interface circuit, the mouse free to move about a substantial plane to produce signals for transmission to the interface circuit and (3) a mouse tray member movably mounted to the chassis and capable of assuming a deployed position whereby the mouse tray extends substantially out of the chassis footprint, a substantially planar surface of the mouse tray providing an area on which the mouse is free to move to produce the signals, the mouse tray member further capable of assuming a stowed position whereby the mouse tray is retracted substantially to within the chassis footprint.