Patents by Inventor Frank Parrish

Frank Parrish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11862901
    Abstract: An interposer for a test system includes coaxial cables, each of which is configured to transport a first portion of current originating from a current source, and printed circuit boards (PCBs), each of which is connected to a set of the coaxial cables in order to receive the first portion of the current from each coaxial cable in the set and to transport a second portion of the current. A spring leaf assembly includes spring leaves, each of which is connected to a PCB in order to transport a third portion of the current obtained from the PCB to a device interface board (DIB) that connects to devices under test (DUTs) to be tested by the test system. The coaxial cables on each PCB are arranged in parallel, the PCBs are arranged in parallel, and the spring leaves on each PCB are arranged in parallel.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: January 2, 2024
    Assignee: TERADYNE, INC.
    Inventors: Frank Parrish, Diwakar Saxena, Michael Herzog, Edward Dague, Michael F. Halblander
  • Patent number: 11651910
    Abstract: An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: May 16, 2023
    Assignee: TERADYNE, INC.
    Inventors: Frank Parrish, Diwakar Saxena, Michael Herzog, Edward Patrick Dague
  • Publication number: 20220189712
    Abstract: An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Inventors: Frank Parrish, Diwakar Saxena, Michael Herzog, Edward Patrick DAGUE
  • Publication number: 20220190527
    Abstract: An interposer for a test system includes coaxial cables, each of which is configured to transport a first portion of current originating from a current source, and printed circuit boards (PCBs), each of which is connected to a set of the coaxial cables in order to receive the first portion of the current from each coaxial cable in the set and to transport a second portion of the current. A spring leaf assembly includes spring leaves, each of which is connected to a PCB in order to transport a third portion of the current obtained from the PCB to a device interface board (DIB) that connects to devices under test (DUTs) to be tested by the test system. The coaxial cables on each PCB are arranged in parallel, the PCBs are arranged in parallel, and the spring leaves on each PCB are arranged in parallel.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Inventors: Frank Parrish, Diwakar Saxena, Michael Herzog, Edward Dague, Michael F. Halblander
  • Patent number: 10677815
    Abstract: An example test system has resources that are distributed for access by a device under test (DUT). The example test system includes a device interface board (DIB) having sites to connect to devices to test, and a tester having slots configured to hold test instruments. Each test instrument has resources that are distributed over a dimension of the DIB. The resources are distributed to enable the devices in the sites equal access to the resources.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: June 9, 2020
    Assignee: Teradyne, Inc.
    Inventors: Mohamadreza Ray Mirkhani, Kevin P. Manning, Roya Yaghmai, Timothy Lee Farris, Frank Parrish
  • Publication number: 20190377007
    Abstract: An example test system has resources that are distributed for access by a device under test (DUT). The example test system includes a device interface board (DIB) having sites to connect to devices to test, and a tester having slots configured to hold test instruments. Each test instrument has resources that are distributed over a dimension of the DIB. The resources are distributed to enable the devices in the sites equal access to the resources.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 12, 2019
    Inventors: Mohamadreza Ray Mirkhani, Kevin P. Manning, Roya Yaghmai, Timothy Lee Farris, Frank Parrish
  • Patent number: 7701232
    Abstract: A semiconductor wafer prober is configured to rotate a semiconductor wafer into relative alignment with a wafer-interface probe adapted to simultaneously probe a number of integrated circuits within a sector of the semiconductor wafer. The wafer can include integrated circuits having different orientations, such that all of the integrated circuits within a given sector being tested have the same orientation. For example, a semiconductor wafer can include two semicircular sectors, with the integrated circuits on either sector having a common orientation rotated 180 degrees from a common orientation of the integrated circuits of the other sector. A wafer-interface probe, or probe card, adapted to test the entire semicircular sector during a single touch down is able to test the entire wafer with one rotational translation between testing.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: April 20, 2010
    Assignee: Teradyne, Inc.
    Inventor: Frank Parrish
  • Publication number: 20080174330
    Abstract: A semiconductor wafer prober is configured to rotate a semiconductor wafer into relative alignment with a wafer-interface probe adapted to simultaneously probe a number of integrated circuits within a sector of the semiconductor wafer. The wafer can include integrated circuits having different orientations, such that all of the integrated circuits within a given sector being tested have the same orientation. For example, a semiconductor wafer can include two semicircular sectors, with the integrated circuits on either sector having a common orientation rotated 180 degrees from a common orientation of the integrated circuits of the other sector. A wafer-interface probe, or probe card, adapted to test the entire semicircular sector during a single touch down is able to test the entire wafer with one rotational translation between testing.
    Type: Application
    Filed: January 23, 2007
    Publication date: July 24, 2008
    Inventor: Frank Parrish
  • Publication number: 20070096755
    Abstract: The traditional device interface board is replaced by a number of smaller strips containing one or more electrical components for interfacing the device under test and the test head. The device interface modules may mount to a stiffening member having a back bone and multiple ribs running through the stiffening member. The device interface strips can create a lattice-like structure for the interface circuitry. Individual circuits may be disposed on the interface strips to perform functionality relating to the device under test and/or the test head.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 3, 2007
    Inventors: Frank Parrish, Derek Castellano, Brian Brecht
  • Publication number: 20070096756
    Abstract: A device for interfacing a test head and a prober is disclosed using wires or cables to provide the connection from a probe card interface boards to the probe card. The use of wires or cables, in place of the traditional pogo pin arrangement allows for more reliable and efficient testing, as well as additional high performance tests to be run. Optionally, a probe interface contains a stiffening member with multiple sidewalks and individual, configuration-specific probe card interface strips are connected to a probe card through zero insertion force clamps. The probe card interface attaches to the test head using standard probe interface board (“PIB”) docking mechanics. The assembly is then connected to a probe to carry out the testing procedures.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 3, 2007
    Inventors: Frank Parrish, Arash Behziz
  • Patent number: 7180321
    Abstract: In one embodiment, a tester interface module for connecting a plurality of signal paths from at least one electronic assembly to at least one other electronic assembly is provided. The interface module includes a capture board having center conductor vias with center conductor holes extending through the capture board. Axial cables secured to the capture board have center conductors extending at least part way through a corresponding center conductor hole of the center conductor via. An interface component is adjacent to the capture board, the conductor paths being conductively bonded to the conductor vias of the capture board so as to electrically connect center conductors to corresponding conductor paths. The conductor paths of the interface component are arranged to allow connection with an electronic assembly.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: February 20, 2007
    Assignee: Teradyne, Inc.
    Inventors: Arash Behziz, Keith Breinlinger, David Evans, Frank Parrish
  • Publication number: 20060071680
    Abstract: In one embodiment, a tester interface module for connecting a plurality of signal paths from at least one electronic assembly to at least one other electronic assembly is provided. The interface module includes a capture board having center conductor vias with center conductor holes extending through the capture board. Axial cables secured to the capture board have center conductors extending at least part way through a corresponding center conductor hole of the center conductor via. An interface component is adjacent to the capture board, the conductor paths being conductively bonded to the conductor vias of the capture board so as to electrically connect center conductors to corresponding conductor paths. The conductor paths of the interface component are arranged to allow connection with an electronic assembly.
    Type: Application
    Filed: September 27, 2005
    Publication date: April 6, 2006
    Inventors: Arash Behziz, David Evans, Frank Parrish, Keith Breinlinger
  • Patent number: 6939175
    Abstract: A coaxial cable for transmitting high frequency signals includes includes a body having a center conductor and a shield formed coaxially around the center conductor and separated from the center conductor by a layer of dielectric having an annular layer of electro-static-discharge polymer. The cable also includes conductive pads to engage contacts on a mating connector. At least one of the conductive pads is attached to the center conductor and at least another one of the conductive pads is attached to the shield.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: September 6, 2005
    Assignee: Teradyne, Inc.
    Inventors: Frank Parrish, Arash Behziz, Derek Castellano, Arthur E. LeColst, Donald Eric Thompson, Jonathan M. Becker
  • Patent number: 6916990
    Abstract: In one embodiment a high power interface apparatus is provided having a multilayer laminated cable including force conductor planes having flush and recessed portions and return conductor planes having flush and recessed portions. The flush portions of the conductor planes extend to a contact end of the laminated cable and the recessed portions are removed from the contact end. The flush portions are aligned along axes at the contact end. The flush portions of the return conductor planes are aligned at the contact end along axes aligned within recessed portions of the force conductor planes. A dielectric material separates the force and return conductor planes. Surface contact pads may be provided on the contact end including force contact pads, each contacting and extending along aligned flush portions of the force conductor planes, and including return conductor pads, each contacting and extending along aligned flush portions of the return conductor planes.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 12, 2005
    Assignee: Teradyne, Inc.
    Inventors: Arash Behziz, Frank Parrish, Donald Thompson, Arthur LeColst, Keith Breinlinger, Brian Brecht, Gerald H. Johnson
  • Publication number: 20040060725
    Abstract: In one embodiment a high power interface apparatus is provided having a multilayer laminated cable including force conductor planes having flush and recessed portions and return conductor planes having flush and recessed portions. The flush portions of the conductor planes extend to a contact end of the laminated cable and the recessed portions are removed from the contact end. The flush portions are aligned along axes at the contact end. The flush portions of the return conductor planes are aligned at the contact end along axes aligned within recessed portions of the force conductor planes. A dielectric material separates the force and return conductor planes. Surface contact pads may be provided on the contact end including force contact pads, each contacting and extending along aligned flush portions of the force conductor planes, and including return conductor pads, each contacting and extending along aligned flush portions of the return conductor planes.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Arash Behziz, Frank Parrish, Donald Thompson, Arthur LeColst, Keith Breinlinger, Brian Brecht, Gerald H. Johnson
  • Patent number: 6686732
    Abstract: An interface module for connecting a plurality of signal paths from a first electronic assembly to a second electronic assembly is disclosed. The interface module includes a plurality of coaxial cables having distal ends adapted for coupling to the first electronic assembly and proximal ends, each cable having a shield conductor and a center conductor. A stiffener formed with a plurality of throughbores receives the proximal ends of the plurality of signal cables, the stiffener having a flat termination side at one end of the plurality of throughbores. The module further includes a signal transition assembly having a flat substrate bonded to the stiffener termination side. The substrate includes respective opposite sides and is formed with spaced-apart signal paths and ground paths extending from one side to the other side.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: February 3, 2004
    Assignee: Teradyne, Inc.
    Inventor: Frank Parrish
  • Publication number: 20030122538
    Abstract: A tester interface assembly is disclosed for coupling a plurality of tester electronic channels to a device-interface-board. The tester interface assembly includes at least one harness assembly having a plurality of coaxial cables, each cable including a body having a center conductor and a shield. The shield is formed coaxially around the center conductor and separated therefrom by a layer of dielectric. Each cable further includes a distal tip formed substantially similar to the body and including respective formed conductive pads disposed on the distal extremities of the center conductor and the shield. The harness employs a housing formed with an internal cavity for receiving and securing the cable distal ends in close-spaced relationship such that the distal tips form an interface engagement plane. A compliant interconnect is interposed between the harness assembly and the device-interface-board, and includes a plurality of conductors formed to engage the cable distal ends along the engagement plane.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 3, 2003
    Applicant: Teradyne, Inc.
    Inventors: Frank Parrish, Arash Behziz, Derek Castellano, Arthur E. LeColst, Donald Eric Thompson, Jonathan M. Becker
  • Publication number: 20030117129
    Abstract: An interface module for connecting a plurality of signal paths from a first electronic assembly to a second electronic assembly is disclosed. The interface module includes a plurality of coaxial cables having distal ends adapted for coupling to the first electronic assembly and proximal ends, each cable having a shield conductor and a center conductor. A stiffener formed with a plurality of throughbores receives the proximal ends of the plurality of signal cables, the stiffener having a flat termination side at one end of the plurality of throughbores. The module further includes a signal transition assembly having a flat substrate bonded to the stiffener termination side. The substrate includes respective opposite sides and is formed with spaced-apart signal paths and ground paths extending from one side to the other side.
    Type: Application
    Filed: December 20, 2001
    Publication date: June 26, 2003
    Inventor: Frank Parrish
  • Patent number: 6515499
    Abstract: A tester interface assembly is disclosed for coupling a plurality of tester electronic channels to a device-interface-board. The tester interface assembly includes at least one harness assembly having a plurality of coaxial cables, each cable including a body having a center conductor and a shield. The shield is formed coaxially around the center conductor and separated therefrom by a layer of dielectric. Each cable further includes a distal tip formed substantially similar to the body and including respective formed conductive pads disposed on the distal extremities of the center conductor and the shield. The harness employs a housing formed with an internal cavity for receiving and securing the cable distal ends in close-spaced relationship such that the distal tips form an interface engagement plane. A compliant interconnect is interposed between the harness assembly and the device-interface-board, and includes a plurality of conductors formed to engage the cable distal ends along the engagement plane.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 4, 2003
    Assignee: Teradyne, Inc.
    Inventors: Frank Parrish, Arash Behziz, Arthur E. LeColst, Derek Castellano, Donald Eric Thompson, Jonathan M. Becker
  • Patent number: 6215320
    Abstract: A multi-level circuit board for efficiently routing electrical signals is disclosed. The circuit board includes a contact layer comprising a first substrate and formed with a set of contact pads disposed across a relatively large surface area. The contact layer also includes a set of engagement contacts corresponding to the contact pads and arrayed in a densely packed surface area. A plurality of subsequent layers are disposed in fixed stacked relationship to the contact layer. Each subsequent layer includes a subsequent substrate, and a conductive pattern formed on the subsequent substrate and defining a plurality of signal paths. Conductive vias are coupled to the contact pads and the engagement contacts and are formed through the contact layer and one or more of the plurality of subsequent layers. The vias communicate with the respective signal paths and include selected sets of staggered vias configured to optimize the routing of the signal paths along the respective subsequent layers.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: April 10, 2001
    Assignee: Teradyne, Inc.
    Inventor: Frank Parrish