Patents by Inventor Frank Prein
Frank Prein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6335228Abstract: A manufacturing process for producing dynamic random access memories (DRAMs) having redundant components includes steps for concurrently forming normal (i.e. non-fused) contacts to components of the DRAMs and anti-fused contacts to the redundant components. The process by which the normal and anti-fused contacts are made is readily implemented using standard integrated circuit processing techniques. An anti-fuse contact (20) and a normal (i.e. non-fused) contact (10) are formed by opening respective contact areas in a dielectric (110), selectively forming an insulating layer (210) over the anti-fuse contact, applying polysilicon (212, 410) to cover the insulating layer of the anti-fuse contact and to fill the opening over the normal contact. In one embodiment of the invention, the circuit region served by the anti-fuse contact is subject to ion implantation (810) to improve its conductivity before the anti-fuse contact is formed.Type: GrantFiled: December 30, 1999Date of Patent: January 1, 2002Assignees: Infineon Technologies North America Corp., White Oak Semiconductor PartnershipInventors: Robert T. Fuller, Frank Prein
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Patent number: 6174741Abstract: Improved techniques for quantifying proximity effects during fabrication of integrated circuits are disclosed. The improved techniques use active features formed on a semiconductor wafer to quantify proximity effects. According to the improved techniques, a device performance quantity for an active feature is measured, and then a feature length for the active feature is determined in accordance with the measured device performance quantity. The fabrication processing can then be evaluated and/or compensated based on the determined feature length. In one example, the active feature can be a metal-oxide semiconductor (MOS) transistor and the device performance quantity can be current.Type: GrantFiled: December 19, 1997Date of Patent: January 16, 2001Assignee: Siemens AktiengesellschaftInventors: Wilfried H{umlaut over (a)}nsch, Frank Prein, J{umlaut over (u)}rgen Faul
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Patent number: 6136677Abstract: A method of fabricating a semiconductor device includes the steps of providing a semiconductor chip (10) with a memory area (22) and a logic area (26). The memory area (22) and the logic area (26) each have gate structures (50) formed therein. The step of sequentially forming silicided junctions (44) in the logic area (26) and implanted junctions in the memory area (26) is also included.Type: GrantFiled: September 25, 1997Date of Patent: October 24, 2000Assignee: Siemens AktiengesellschaftInventor: Frank Prein
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Patent number: 6121074Abstract: A method of fabricating a fuse for a semiconductor memory, in accordance with the invention, includes the steps of forming a gate structure on a substrate including a polysilicon fuse layer and a gate cap layer disposed above the polysilicon fuse layer, forming an interlevel dielectric layer over the gate structure, depositing a dielectric layer over the interlevel dielectric layer, the dielectric layer and the interlevel dielectric layer both including a material which is selectively etchable relative to the gate cap layer and selectively etching contact holes through the dielectric layer and the interlevel dielectric layer such that at least one contact hole is formed over the gate structure and extends into the gate cap layer.Type: GrantFiled: November 5, 1998Date of Patent: September 19, 2000Assignee: Siemens AktiengesellschaftInventor: Frank Prein
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Patent number: 6103592Abstract: FET devices are manufactured using STI on a semiconductor substrate coated with a pad from which are formed raised active silicon device areas and dummy active silicon mesas capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide layer is deposited on the device with conformal projections above the mesas. Then a polysilicon film on the blanket silicon oxide layer is deposited with conformal projections above the mesas. The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer is exposed over the pad structures. Selective RIE partial etching of the conformal silicon oxide layer over the mesas is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride as an etch stop.Type: GrantFiled: May 1, 1997Date of Patent: August 15, 2000Assignees: International Business Machines Corp., Siemens AktiengesellschaftInventors: Max Gerald Levy, Bernhard Fiegl, Walter Glashauser, Frank Prein
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Patent number: 6070004Abstract: A method of fabricating semiconductor chips includes the steps of optimizing a number of chips that geometrically fit on a wafer and maximizing chip yield for the wafer by considering chips located in a normally rejectable location and utilizing yield probability data for the chip in the normally rejectable locations to weight the probability of an acceptable chip such that if the probability is above a threshold value the chips are not rejected. This results in an increased chip yield for semiconductor wafers.Type: GrantFiled: September 25, 1997Date of Patent: May 30, 2000Assignee: Siemens AktiengesellschaftInventor: Frank Prein
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Patent number: 5981302Abstract: A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3.times.3 block of the first pads.Type: GrantFiled: February 23, 1999Date of Patent: November 9, 1999Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Frank Alswede, William Davies, Ronald Hoyer, Ron Mendelson, Frank Prein
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Patent number: 5917197Abstract: A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3.times.3 block of the first pads.Type: GrantFiled: May 21, 1997Date of Patent: June 29, 1999Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Frank Alswede, William Davies, Ronald Hoyer, Ron Mendelson, Frank Prein
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Patent number: 5899706Abstract: In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.Type: GrantFiled: June 30, 1997Date of Patent: May 4, 1999Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Andreas Kluwe, Lars Liebmann, Frank Prein, Thomas Zell
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Patent number: 5608257Abstract: In an integrated circuit having interconnecting lines formed on an insulated layer deposited on a semiconductor substrate which provide connections between elements integral to the integrated circuit, a fuse structure programmable by a laser beam that includes: a melt-away elongated fuse link joining two segments of an interconnecting line; a plurality of fins integral and coplanar to the fuse link, each of the fins transversally extending away from the fuse link for absorbing energy emitted by the laser beam; and a reflecting plate positioned underneath the fuse link to reflect energy provided by the laser beam back into the fuse link, such that both the combination of the fins and the reflecting plate reduces the energy emitted by the laser beam required to blow the fuse structure.Type: GrantFiled: June 7, 1995Date of Patent: March 4, 1997Assignee: International Business Machines CorporationInventors: Pei-Ing P. Lee, Frank Prein