Abstract: An abrupt drain junction and a graded source junction are fabricated using a common diffusion step, wherein the common diffusion step is used to create both the drain junction-and the source junction. The common diffusion step is accomplished while an oxide spacer is present over a gate stack, prior to the common diffusion step, resulting in faster source diffusion and a graded source junction, while the slower diffusion in the drain region results in an abrupt drain junction. The oxide spacer moves the drain junction further away from the gate stack to allow for greater cell densities.

Abstract: An abrupt drain junction and a graded source junction are fabricated using a common diffusion step, wherein the common diffusion step is used to create both the drain junction-and the source junction. The common diffusion step is accomplished while an oxide spacer is present over a gate stack, prior to the common diffusion step, resulting in faster source diffusion and a graded source junction, while the slower diffusion in the drain region results in an abrupt drain junction. The oxide spacer moves the drain junction further away from the gate stack to allow for greater cell densities.

Abstract: An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.

Abstract: An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.