Abstract: A node controller for a first processor socket group may include a node memory storing a coherence directory and logic. Logic may cause the node controller to: receive a memory operation request directly from a second processor socket group, follow a coherence protocol based on the memory operation request and the coherence directory and directly access a socket group memory of the first processor socket group based on the request.

Abstract: A first node controller may include logic to direct the first node controller to: receive a noncoherent inter-processor communication from a source processor, remap the noncoherent inter-processor communication to a local address space of a destination processor and transmit the noncoherent inter-processor communication directly to a second node controller of the destination processor using an interconnect interface that also carries coherent communications.

Abstract: A first node controller may include logic to direct the first node controller to: receive a noncoherent inter-processor communication from a source processor, remap the noncoherent inter-processor communication to a local address space of a destination processor and transmit the noncoherent inter-processor communication directly to a second node controller of the destination processor using an interconnect interface that also carries coherent communications.

Abstract: A node controller to manage access to and provide responses from a remote memory for a plurality of processor nodes. A learning block monitors requests to a given data block in the remote memory and monitors parameters associated with the requests. The learning block updates a respective weighting value for each of the parameters associated with the requests to the given data block. Event detection circuitry stores the parameters and the weighting values for each of the parameters associated with an address for the given data block to determine a subsequent memory action for the prospective data block in the remote memory.

Abstract: A system includes a volatile memory to store data and a memory controller to manage the data in the volatile memory. The memory controller includes an inner code generator to generate a respective inner correction code for each of a plurality of blocks of the data in the volatile memory. An outer code generator generates an outer correction code based on the plurality of blocks of the data. The memory controller updates the outer correction code as part of a refresh to the plurality of blocks of the data in the volatile memory.

Abstract: A system, method, and storage medium provide dynamic, packet-based adaptive forward error correction over a lossy bidirectional data communication medium that couples a transmitting device to a receiving device. The transmitting device repeatedly transmits encoded data packets formed by applying, to unencoded data, a forward error correction (FEC) algorithm having a level N that indicates a number of correctable errors. The receiving device attempts to decode the encoded data packets using the FEC algorithm, requesting retransmission of a packet if there are too many errors to correct. The transmitting device decreases the level N when it does not receive such a request within a given duration. By contrast, the transmitting device increases the level N when it receives a sequence of such requests having a threshold length, each request being received less than the given duration after the previous request.

Abstract: A high-performance computing system, method, and storage medium manage accesses to multiple memory modules of a computing node, the modules having different access latencies. The node allocates its resources into pools according to pre-determined memory access criteria. When another computing node requests a memory access, the node determines whether the request satisfies any of the criteria. If so, the associated pool of resources is selected for servicing the request; if not, a default pool is selected. The node then services the request if the pool of resources is sufficient. Otherwise, various error handling processes are performed. Each memory access criterion may relate to a memory address range assigned to a memory module, a type of request, a relationship between the nodes, a configuration of the requesting node, or a combination of these.

Abstract: A system, method, and storage medium provide dynamic, packet-based adaptive forward error correction over a lossy bidirectional data communication medium that couples a transmitting device to a receiving device. The transmitting device repeatedly transmits encoded data packets formed by applying, to unencoded data, a forward error correction (FEC) algorithm having a level N that indicates a number of correctable errors. The receiving device attempts to decode the encoded data packets using the FEC algorithm, requesting retransmission of a packet if there are too many errors to correct. The transmitting device decreases the level N when it does not receive such a request within a given duration. By contrast, the transmitting device increases the level N when it receives a sequence of such requests having a threshold length, each request being received less than the given duration after the previous request.

Abstract: In one aspect a system is provided. The system a plurality of flash compare modules to output a set of unordered output signals based on an analog input signal; a plurality of device selection modules that receive the unordered output signals and generate ordered signals representing the analog input; and a temperature and voltage compensation module for receiving one or more of temperature and voltage signals from at least a temperature and voltage sensor module that senses one or more of temperature and voltage values that are used to compensate for changes in output signals caused by changes in one or more of die temperature and core voltage.

Abstract: A memory device may include a memory unit having multiple channel structures connected to a common source and drain in parallel. The memory unit can include floating gate structures including control gates connected to word lines and charge trap layers to store charge to form tiered floating gate memory cells. In some embodiments, rows and columns of memory units can be connected to form a three dimensional memory device. A method of fabricating a memory unit having tiered channel structures utilizing common source and drain elements and 3D memory device utilizing rows and columns of memory units having multiple channel structures connected to the common source and drain elements in parallel is disclosed.

Abstract: In one aspect a system is provided. The system a plurality of flash compare modules to output a set of unordered output signals based on an analog input signal; a plurality of device selection modules that receive the unordered output signals and generate ordered signals representing the analog input; and a temperature and voltage compensation module for receiving one or more of temperature and voltage signals from at least a temperature and voltage sensor module that senses one or more of temperature and voltage values that are used to compensate for changes in output signals caused by changes in one or more of die temperature and core voltage.

Abstract: Methods and systems for a network device are provided. The network device includes a stage one arbiter for a base-port having a plurality of sub-ports for determining if there are any pending requests; blocking any other requests from a same receive queue destined for a same sub-port, same transmit queue when there are any pending requests; selecting a group of requests with a highest priority and available resources; selecting highest priority requests; selecting an oldest one of the highest priority requests; sending the selected requests to a stage two arbiter for selecting a request with a highest priority and when there are requests that have a same priority, selecting an oldest request for processing.

Abstract: Methods and systems for a network device. The network device includes a temporary memory storage device having a plurality of storage locations that are used to store packets received by a plurality of sub-ports. The network device includes a cut-through estimation circuit that estimates a cut-through threshold value based on which a certain portion of a packet has to be received and stored at one of the plurality of storage locations before the packet can be processed by one of the sub-ports that received the frame. The cut-through threshold value varies based on an operating speed of a network link the packet is received on, an operating speed of a network link the packet is transmitted on, and a protocol used for receiving and transmitting the packet.

Abstract: A key-value storage device and method of using the same. In some embodiments, keys are stored in a key store in a first non-volatile memory and corresponding values associated with the keys are stored in a value store of a second non-volatile memory. An input command is received from a host device, the input command having a key associated with a value. Different first and second hash values are generated by applying a hash function to the key. The input command is executed responsive to the first and second hash values.

Abstract: A network device and associated methods are provided. The network device includes a routing module having a ternary content addressable memory (TCAM) module maintained for storing a plurality of entries for routing frames that are received for a plurality of sub-ports complying with a plurality of protocols; a steering action memory that stores a plurality of steering action codes associated with the plurality of TCAM entries for tossing frames, rejecting frames and providing them to a processor for the network device, indicating that a destination is valid, and indicating to use another routing mechanism; and a steering mechanism that is used when a received frame information does not match with the TCAM entries and the received frame is of a certain protocol type.

Abstract: Machine-implemented method for a network device is provided. A temperature (T) of an application specific integrated circuit (ASIC) for the network device is compared with a first threshold value. A receive buffer for the network device is placed in an active state, when T is below the first threshold value, and then increasing available credit to store information at the receive buffer. T is also compared with a second threshold value and when T has reached or exceeded the second threshold value, one or more receive buffers are placed in a reduced power state when one or more receive buffers are not currently storing any information.

Abstract: A key-value storage device and method of using the same. In some embodiments, keys are stored in a key store in a first non-volatile memory and corresponding values associated with the keys are stored in a value store of a second non-volatile memory. An input command is received from a host device, the input command having a key associated with a value. Different first and second hash values are generated by applying a hash function to the key. The input command is executed responsive to the first and second hash values.

Abstract: Method and system for a network device are provided. The device includes a port for receiving a multicast packet and a multicast data structure for maintaining information regarding a multicast group to which the multicast packet is to be sent. When the port is a part of a link aggregation group (LAG), then any port that is a member of the LAG is removed from the multicast group such that the multicast packet is not sent to any member of the LAG.

Abstract: Method and system for configuring a port of a network device are provided. One method for a port of a network device communicating with another network device port includes reading manufacturing, license and user provided port configuration data by a processor of the network device; obtaining capabilities information for the port by the processor of the network device from an external pluggable media device; setting port configuration data based on the capabilities information obtained from the external pluggable media; executing auto-negotiation on the port, when enabled and obtaining configuration data from the other port; determining that enough data is available to set port configuration; attempting to configure the port by using a highest permissible bandwidth configuration when enough data is available to set the port configuration; and setting port configuration based on the attempt to configure the port to operate when a link connected to the port is operational.

Abstract: Network device and associated methods are provided. The network device includes a plurality of base-ports, each base-port coupled to a plurality of network links and each base-port includes a plurality of sub-ports configured to operate as independent ports for sending and receiving information. Each network link is coupled to a smoothing first in-first out (FIFO) memory module that is used to temporarily store information at a first clock rate and information is read from the smoothing FIFO at a second clock. A sub-port can include one network link or more than one network link for receiving information from another device. A controller module monitors the smoothing FIFO for each network link to insert or delete characters from each of the smoothing FIFO based on a sub-port configuration for maintaining an order in which information is received for the sub-port.