Patents by Inventor Frank R. Kschischang
Frank R. Kschischang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10944430Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: GrantFiled: January 3, 2020Date of Patent: March 9, 2021Assignee: INPHI CORPORATIONInventors: Arash Farhoodfar, Frank R. Kschischang, Benjamin P. Smith, Andrew Hunt
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Publication number: 20200145027Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: ApplicationFiled: January 3, 2020Publication date: May 7, 2020Inventors: Arash FARHOODFAR, Frank R. KSCHISCHANG, Benjamin P. SMITH, Andrew HUNT
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Patent number: 10601449Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: September 18, 2019Date of Patent: March 24, 2020Assignee: INPHI CORPORATIONInventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Patent number: 10567005Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: GrantFiled: September 18, 2018Date of Patent: February 18, 2020Assignee: INPHI CORPORATIONInventors: Arash Farhoodfar, Frank R. Kschischang, Benjamin P. Smith, Andrew Hunt
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Publication number: 20200014407Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: September 18, 2019Publication date: January 9, 2020Applicant: INPHI CORPORATIONInventors: Benjamin SMITH, Arash FARHOODFAR, Stewart CROZIER, Frank R. KSCHISCHANG, Andrew HUNT
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Patent number: 10461781Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: June 18, 2018Date of Patent: October 29, 2019Assignee: INPHI CORPORATIONInventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Patent number: 10320425Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.Type: GrantFiled: June 27, 2016Date of Patent: June 11, 2019Assignee: INPHI CORPORATIONInventors: Arash Farhoodfar, Frank R. Kschischang, Andrew Hunt, Benjamin P. Smith, John Lodge
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Publication number: 20190020356Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: ApplicationFiled: September 18, 2018Publication date: January 17, 2019Inventors: Arash FARHOODFAR, Frank R. KSCHISCHANG, Benjamin P. SMITH, Andrew HUNT
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Patent number: 10110252Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: GrantFiled: December 14, 2016Date of Patent: October 23, 2018Assignee: INPHI CORPORATIONInventors: Arash Farhoodfar, Frank R. Kschischang, Benjamin P. Smith, Andrew Hunt
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Publication number: 20180302108Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: June 18, 2018Publication date: October 18, 2018Inventors: Benjamin SMITH, Arash FARHOODFAR, Stewart CROZIER, Frank R. KSCHISCHANG, Andrew HUNT
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Patent number: 10033410Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: July 8, 2016Date of Patent: July 24, 2018Assignee: INPHI CORPORATIONInventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Publication number: 20170093436Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: ApplicationFiled: December 14, 2016Publication date: March 30, 2017Inventors: Arash Farhoodfar, Frank R. Kschischang, Benjamin P. Smith, Andrew Hunt
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Patent number: 9564926Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: GrantFiled: November 13, 2014Date of Patent: February 7, 2017Assignee: CORTINA SYSTEMS, INC.Inventors: Arash Farhoodfar, Frank R. Kschischang, Benjamin P. Smith, Andrew Hunt
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Publication number: 20160322989Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: July 8, 2016Publication date: November 3, 2016Inventors: Benjamin SMITH, Arash FARHOODFAR, Stewart CROZIER, Frank R. KSCHISCHANG, Andrew HUNT
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Publication number: 20160308558Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: Arash Farhoodfar, Frank R. Kschischang, Andrew Hunt, Benjamin P. Smith, John Lodge
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Patent number: 9413493Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: June 18, 2015Date of Patent: August 9, 2016Assignee: Cortina Systems, Inc.Inventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Patent number: 9397702Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.Type: GrantFiled: April 30, 2014Date of Patent: July 19, 2016Assignee: Cortina Systems, Inc.Inventors: Arash Farhoodfar, Frank R. Kschischang, Andrew Hunt, Benjamin P. Smith, John Lodge
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Publication number: 20150288485Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Patent number: 9083492Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: February 13, 2014Date of Patent: July 14, 2015Assignee: Cortina Systems, Inc.Inventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Publication number: 20150074500Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: ApplicationFiled: November 13, 2014Publication date: March 12, 2015Inventors: Arash Farhoodfar, Frank R. Kschischang, Benjamin P. Smith, Andrew Hunt