Patents by Inventor Frank Ray Keyser, III
Frank Ray Keyser, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6373906Abstract: Apparatus is provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. The two-way add/compare/select includes a two-way compare for comparing first and second state metric input values and a pair of two-way adds in parallel with the two-way compare for respectively adding the first and second state metric input values with a second input value. The second input value includes a time varying term or a constant term. The time varying terms are expressed as outputs Zn of a partial matched filter or as outputs Wn of a matched filter. A multiplexer is coupled to the pair of two-way adds, the multiplexer receiving a selectable input controlled by the two-way compare. A pair of shifts coupled between the pair of two-way adds and the multiplexer receive a shift control input for providing metric bounding to avoid underflow.Type: GrantFiled: January 24, 2001Date of Patent: April 16, 2002Assignee: International Business Machines CorporationInventors: Roy Daron Cideciyan, Jonathan Darrel Coker, Evangelos S. Eleftheriou, Richard Leo Galbraith, Allen Prescott Haar, Frank Ray Keyser, III, David James Stanek
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Patent number: 6233191Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: February 22, 2000Date of Patent: May 15, 2001Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III
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Patent number: 6130854Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: October 10, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch
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Patent number: 6118707Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 10, 1998Date of Patent: September 12, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch
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Patent number: 6075745Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: June 13, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 6044031Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: March 28, 2000Assignee: International Business Machines CorporationInventors: Joseph Andrew Iadanza, Frank Ray Keyser, III
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Patent number: 6038192Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 10, 1998Date of Patent: March 14, 2000Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Joseph Andrew Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 6023421Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: February 8, 2000Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 6021513Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.Type: GrantFiled: October 28, 1998Date of Patent: February 1, 2000Assignee: International Business Machines CorporationInventors: Wayne Kevin Beebe, Sally Botala, Scott Whitney Gould, Frank Ray Keyser, III, Wendell Ray Larsen, Ronald Raymond Palmer, Brian Worth
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Patent number: 5949719Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: September 7, 1999Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 5910733Abstract: A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.Type: GrantFiled: November 12, 1997Date of Patent: June 8, 1999Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P.N. Clinton, Scott Whitney Gould, Frank Ray Keyser III, Timothy Shawn Reny, Terrance John Zittritsch
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Patent number: 5867507Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.Type: GrantFiled: December 12, 1995Date of Patent: February 2, 1999Assignee: International Business Machines CorporationInventors: Wayne Kevin Beebe, Sally Botala, Scott Whitney Gould, Frank Ray Keyser III, Wendell Ray Larsen, Ronald Raymond Palmer, Brian Worth
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Patent number: 5836007Abstract: A memory system having split logical bit lines and interleaved pre-charge/access cycles is provided. A bit line access circuit supports multiple conductors per logical bit line and pre-charges the conductors before access cycles thereto. The access cycles for one logical bit line are performed simultaneous with the pre-charge cycles for another logical bit line by the access circuit. Virtual reading is provided for eliminated memory cells. The memory system can be used in a programmable gate array having memory cells distributed throughout for programming respective programmable resources.Type: GrantFiled: September 14, 1995Date of Patent: November 10, 1998Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Frank Ray Keyser III, Wendell Ray Larsen
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Patent number: 5802003Abstract: A system is provided for providing functional, initialization and reset access to a plurality of memory cells of a memory array, using a single cell write port and a single cell read port. In addition to functional address and data buses, initialization address and data buses are provided. The invention is disclosed in association with a field-programmable memory array having multiple sub-arrays therein. The address units for each sub-array are provided to programmably provide address information to the wordlines of each sub-array from an initialization address bus or a functional address bus. Similarly, readhead and writehead circuits within each sub-array are also programmable to propagate data between initialization or functional data buses and the memory cells of the sub-array. The address units, readheads, and writeheads are all responsive to a dominant reset signal to reset the associated cells.Type: GrantFiled: December 20, 1995Date of Patent: September 1, 1998Assignee: International Business Machines CorporationInventors: Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie
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Patent number: 5745734Abstract: A generalized data decompression engine is incorporated within a field programmable gate array ("FPGA"). The generalized data decompression engine uses a general purpose data decompression technique such as, for example, a Lempel-Ziv type technique. During operation, a compressed configuration bit stream is received by the generalized data decompression engine in the FPGA and is decompressed thereby. A resultant decompressed configuration bit stream is then used to program logic cells within the FPGA.Type: GrantFiled: September 29, 1995Date of Patent: April 28, 1998Assignee: International Business Machines CorporationInventors: David John Craft, Scott Whitney Gould, Frank Ray Keyser, III, Brian Worth
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Patent number: 5734582Abstract: A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.Type: GrantFiled: December 12, 1995Date of Patent: March 31, 1998Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P. N. Clinton, Scott Whitney Gould, Frank Ray Keyser, III, Timothy Shawn Reny, Terrance John Zittritsch
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Patent number: 5732246Abstract: A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal.Type: GrantFiled: June 7, 1995Date of Patent: March 24, 1998Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Frank Ray Keyser, III, Wendell Ray Larsen, Brian Allen Worth
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Patent number: 5717346Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.Type: GrantFiled: September 6, 1996Date of Patent: February 10, 1998Assignees: International Business Machines Corporation, Atmel CorporationInventors: Scott Whitney Gould, Frederick Curtis Furtek, Frank Ray Keyser, III, Brian A. Worth, Terrance John Zittritsch
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Patent number: 5703498Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.Type: GrantFiled: September 6, 1996Date of Patent: December 30, 1997Assignees: International Business Machines Corporation, Atmel CorporationInventors: Scott Whitney Gould, Frederick Curtis Furtek, Frank Ray Keyser, III, Brian A. Worth, Terrance John Zittritsch
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Patent number: 5652529Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.Type: GrantFiled: June 2, 1995Date of Patent: July 29, 1997Assignees: International Business Machines Corporation, Atmel CorporationInventors: Scott Whitney Gould, Frederick Curtis Furtek, Frank Ray Keyser, III, Brian A. Worth, Terrance John Zittritsch