Abstract: A 2D microfluidic structure for capacitance sensing of analyte is provided. The structure includes a first substrate located above at least one microfluidic channel, and a second substrate located below the at least one microfluidic channel. The first substrate includes at least one first group of three isolated electrodes and the second substrate includes at least one second group of three isolated electrodes, where each group of isolated electrodes includes a ground electrode and two probe electrodes.

Abstract: A system is for in-situ monitoring and recording of fish health of fish in a fish cage. The system has at least one camera housing. The camera housing is provided with a camera group having at least two cameras arranged to take synchronized pictures for digital close-range photogrammetry. The system has a central data-processing unit, the central data-processing unit being arranged to calculate a three-dimensional model of an object photographed synchronously by the at least two cameras. The data-processing unit is arranged to report the number of structures deviating from the smooth surface of the object in the three-dimensional model.

Abstract: A linear microfluidic device for sensing, e.g., capacitance sensing, of one or more substances of interest (i.e., one or more analytes) is provided. The linear microfluidic device has a linear microfluidic channel that includes at least one microfluidic sensing cell located along the linear microfluidic channel. The at least one microfluidic sensing cell includes an upper electrode portion that is vertically spaced apart from a lower electrode portion, and each of the upper electrode portion and the lower electrode portion includes at least one electrically isolated probe electrode.

Abstract: A 2D microfluidic structure for capacitance sensing of analyte is provided. The structure includes a first substrate located above at least one microfluidic channel, and a second substrate located below the at least one microfluidic channel. The first substrate includes at least one first group of three isolated electrodes and the second substrate includes at least one second group of three isolated electrodes, where each group of isolated electrodes includes a ground electrode and two probe electrodes.

Abstract: An impedance sensing structure is provided and includes a dielectric layer, a spiral electrode pair forming a dual spiral channel on the dielectric layer and having an inlet portion at a central region of the dual spiral channel and an outlet portion at an end of the dual spiral channel, inlet and outlet elements and sensing circuitry. The inlet and outlet elements are coupled with the inlet and outlet portions, respectively, for directing fluid or gas to flow through the dual spiral channel. The sensing circuitry is electrically connected with the spiral electrode pair and configured to sense the particles in the fluid or gas in accordance with an impedance of the spiral electrode pair and the fluid or gas flowing through the dual spiral channel.

Abstract: Devices and methods for detecting the presence and/or monitoring a movement of an analyte contained in a medium. More specifically, a microcapacitive sensing system is provided that includes a planar micro-capacitive sensor array for detecting the presence of an analyte in a sample media. The sensor structure for sensing recognizing or tracking material movement includes a top planar substrate having a first array non-contacting planar conductive electrodes and a bottom planar substrate having a second array of non-contacting planar conductive electrodes overlapping corresponding aligned electrodes in the first array. The overlapping conducting electrodes are triangular shaped to maximize perimeter-to-area ratio. The first and second planar substrates are parallel and sealed to define a volume therebetween for receiving a medium including the analyte to be detected or monitored.

Abstract: Alignment and etch bias structures are provided that accomplish (I) a single alignment/monitor pattern for multiple layers, (II) the functions of precision alignment marks, course alignment marks, and characterization alignment/monitoring marks, (III) in-situ post fabrication characterization by at least two methods, optical and electrical (e.g., capacitance) with one pattern, and (IV) detects not only alignment/misalignment quality, but also layer over-etch precision, intra-wafer intra printed circuit board (PCB) distortion, and intra-layer dielectric characteristics.

Abstract: A sensing structure is provided and includes a tubular element through which a fluid is flowable along a single path, an array of sensors disposed along a length of the tubular element whereby the fluid is flowable through each of the sensors and sensing circuitry electrically connected with each of the sensors and configured to measure a reactance of each of the sensors and to determine whether any reactance is indicative of a presence of a biological cell in the fluid flowing through the corresponding sensors.

Abstract: Compound semiconductor and silicon-based structures are epitaxially formed on semiconductor substrates and transferred to a carrier substrate. The transferred structures can be used to form discrete photovoltaic and light-emitting devices on the carrier substrate. Silicon-containing layers grown on doped donor semiconductor substrates and compound semiconductor layers grown on off-cut semiconductor substrates form elements of the devices. The carrier substrates may be electrically insulating substrates or include electrically insulating layers to which photovoltaic and/or light-emitting structures are bonded.

Abstract: A chip and cooler assembly includes an active or passive interposer that has a front side and a back side. Integrated circuit chips are mounted onto the back side of the interposer. Each of the chips has a front side that is attached to the interposer and a back side that faces away from the interposer. Gaps separate the chips. The assembly also includes a frame that is fitted into the gaps between the chips. The frame is CTE-matched to the chips. The frame and the chips define a back side surface. A cooler module is attached to the back side surface. The cooler module is CTE-matched to the chips. The cooler module includes a microchannel cooler that is disposed directly against the back sides of the chips and a manifold that is attached to the microchannel cooler opposite the chips. The manifold is CTE-matched to the microchannel cooler.

Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

Abstract: Techniques are provided for intra-bonding multiple semiconductor integrated circuit chips to form multi-chip package structures. For example, a device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first overlap region which comprises a first array of metallic contacts. The second semiconductor die comprises a second overlap region which comprises a second array of metallic contacts. The first overlap region and the second overlap region are overlapped and bonded together with the first array of metallic contacts aligned to the second array of metallic contacts, and with the first semiconductor die and the second semiconductor die disposed laterally adjacent to each other.

Abstract: A capacitive probe structure is presented including two or more microfluidic channels defined within a plurality of dielectric layers disposed over a substrate, and a plurality of probes extending through the plurality of dielectric layers such that several probes of the plurality of probes extend to the two or more microfluidic channels to measure at least particle concentrations and particle flow within the two or more microfluidic channels. The plurality of probes are physically and electrically isolated from each other by the plurality of dielectric layers. The plurality of probes further measure a dielectric constant change for conducting and non-conducting liquids and gasses within the two or more microfluidic channels.

Abstract: A bridge chip of an IC packaging structure includes E/O and O/E converters and a first wiring pattern interconnecting the converters to host chips and a second wiring pattern electrically connected to the host chips. An optical interface outputs the optical signals from a backside surface of the bridge chip. The optical interface receives optical signals through the backside surface. Electrical through links connected to the second wiring pattern output electrical signals generated by the host chips through the backside surface of the bridge chip. The packaging structure includes substrate with a trench provided in the top surface of the substrate and the bridge chip disposed in the trench. The host chips are directly connected to the top surface of the bridge chip and the top surface of the substrate. Optical signals are output from the packaging structure through an opening in the bottom surface of the substrate.

Abstract: A device and associated method include using an optical element (OE) for electrical and optical communications on the device. A substrate includes a wiring layer with an optically transparent path which allows optical signals to pass therethrough. An optical coupling layer is coupled to the wiring layer, and the optical coupling layer includes at least one micro-lens for focusing or collimating the optical signals through the transparent path. An OE is coupled to the wiring layer, and the OE is positioned in optical alignment with the optically transparent path for communicating optical signals. One or more semiconductor chips can be communicatively coupled to an OE for controlling the OE.

Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

Abstract: Systems and processes for operating an intelligent automated assistant are provided. In one example, a user request for a media item is received. Based on the user request, at least one media item and a description of the at least one media item are identified. A confidence level is obtained that an identified media item of the at least one media item corresponds to the requested media item. In accordance with a determination that the confidence level exceeds a first confidence threshold, a length of the identified description is reduced to obtain a modified description and the modified description of the identified media item is provided in a first spoken response.

Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

Abstract: Compound semiconductor and silicon-based structures are epitaxially formed on semiconductor substrates and transferred to a carrier substrate. The transferred structures can be used to form discrete photovoltaic and light-emitting devices on the carrier substrate. Silicon-containing layers grown on doped donor semiconductor substrates and compound semiconductor layers grown on off-cut semiconductor substrates form elements of the devices. The carrier substrates may be electrically insulating substrates or include electrically insulating layers to which photovoltaic and/or light-emitting structures are bonded.

Abstract: A multidimensional multilevel coding (MLC) encoder comprises a soft forward error correction (FEC) encoder receiving first bits for generating soft FEC encoded bits, a redundancy generator receiving a subset of the soft FEC encoded bits for generating redundant bits, and a hard FEC encoder receiving second bits for generating hard FEC encoded bits. Combinations of the soft FEC encoded bits, the redundant bits, and the hard FEC encoded bits form labels for mapping to a plurality of constellation points. A MLC decoder comprises a redundancy decoder, a soft FEC decoder and a hard FEC decoder. The redundancy decoder combines log-likelihood-ratios (LLR) of soft FEC encoded bits received from the MLC encoder to allow the soft FEC decoder to produce decoded bits. Decoding of hard FEC encoded bits by the hard FEC decoder is conditioned on values of the bits decoded by the soft FEC decoder.