Patents by Inventor Frank S Geefay

Frank S Geefay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8102044
    Abstract: A method of packaging electronics comprises providing a first wafer and providing a second wafer. The method also comprises depositing a polymer material over a surface of the first wafer; and selectively removing a portion of the polymer from the first wafer to create a void in the polymer. The method also comprises placing the first wafer over the second wafer and in contact with the polymer; and curing the polymer to bond the first wafer to the second wafer. A bonded wafer structure is also described.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: January 24, 2012
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Richard C. Ruby, James P. Roland, Frank S. Geefay
  • Publication number: 20100096745
    Abstract: A method of packaging electronics comprises providing a first wafer and providing a second wafer. The method also comprises depositing a polymer material over a surface of the first wafer; and selectively removing a portion of the polymer from the first wafer to create a void in the polymer. The method also comprises placing the first wafer over the second wafer and in contact with the polymer; and curing the polymer to bond the first wafer to the second wafer. A bonded wafer structure is also described.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 22, 2010
    Applicant: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Richard Ruby, James P. Roland, Frank S. Geefay
  • Patent number: 7554177
    Abstract: An attachment system. The attachment system includes a first structure and a second structure. The first structure has a surface and a recess in the surface. The second structure is molded into the recess and extends above the surface. The second structure adheres to the first structure at a boundary of the recess.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: June 30, 2009
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Frank S. Geefay, David T. Dutton, Qing Bai
  • Publication number: 20080283944
    Abstract: A Film Bulk Acoustic (FBA) MEMS device in a wafer level package including a photostructurable glass material and methods of manufacture are described.
    Type: Application
    Filed: May 18, 2007
    Publication date: November 20, 2008
    Inventor: Frank S. Geefay
  • Patent number: 7422929
    Abstract: In an embodiment, the invention provides a method for forming a wafer-level package. A bonding pad is formed on a first wafer. After forming the bonding pad, an optoelectronic device is located on the first wafer. A gasket is formed on a second wafer. After a gasket is formed on a second wafer, the second wafer is attached to the first wafer with a bond between the gasket and the bonding pad.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: September 9, 2008
    Assignee: Avago Technologies Fiber IP Pte Ltd
    Inventors: Kendra J. Gallup, Frank S. Geefay, Ronald Shane Fazzio, Martha Johnson, Carrie Ann Guthrie, Tanya Jegeris Snyder, Richard C. Ruby
  • Patent number: 7161283
    Abstract: A device includes a device substrate defining a pit in a topside of the device substrate, a film bulk-wave acoustic resonator (FBAR) mounted over the pit on the device substrate, a first contact pad on a backside of the device substrate that is coupled to a bottom electrode of the FBAR, and a second contact pad on the backside of the device substrate that is coupled to a top electrode of the FBAR.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 9, 2007
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventor: Frank S. Geefay
  • Patent number: 6979597
    Abstract: A gasket encloses a hermetically sealed environment between a cap wafer and a base wafer. The gasket is bonded to the base wafer using bonding material. The bonding material can be one or more of many substances that exhibit acceptable adhesion, sealing, and other properties that ensure a hermetically sealed environment. The gasket is carved out from the cap wafer material itself. The cap wafer is typically made of extremely strong and rigid material such as silicon. Since the gasket is made from the cap wafer, the gasket itself is also extremely strong and rigid.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: December 27, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Frank S Geefay, Qing Gan, Ann Mattos, Domingo A Figueredo
  • Patent number: 6953990
    Abstract: A wafer-level package includes a first wafer comprising a bonding pad, an optoelectronic device on the first wafer, and a second wafer comprising a gasket. The second wafer is attached to the first wafer by a bond between the gasket and the bonding pad.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: October 11, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Kendra J. Gallup, Frank S. Geefay, Ronald Shane Fazzio, Martha Johnson, Carrie Ann Guthrie, Tanya Jegeris Snyder, Richard C. Ruby
  • Patent number: 6919222
    Abstract: An apparatus includes a device chip having circuit elements fabricated on a substrate and a cap covering at least a portion of the device chip including the circuit elements such as thin film resonators. The placement of the cap on the device chip is sealed using a gasket having treaded surface for improved adhesion, cold weld deformation of gold, and decreased susceptibility to foreign particles resulting in a superior seal.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: July 19, 2005
    Assignee: Agilent Technologies, Inc.
    Inventor: Frank S. Geefay
  • Patent number: 6903012
    Abstract: A sloped via contact is used to connect a contact on the front side of a wafer to a contact on the back side of the wafer. The walls of a small (less than 50-80 microns wide) via have typically been difficult to coat with metal. The present invention forms a small via with sloped walls, allowing easy access to the inside walls of the via for metal sputtering or plating. The small via can be formed using a dry etch process such as the well-known deep reactive ion etching (DRIE) process. Using any isotropic plasma etch process, the walls of the via are further etched from the wafer backside to create sloped walls in the via. The via is then coated with metal to make it conductive.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: June 7, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Frank S Geefay, Qing Gan
  • Patent number: 6836013
    Abstract: An apparatus includes a device chip having circuit elements fabricated on a substrate and a cap covering at least a portion of the device chip including the circuit elements such as thin film resonators. The placement of the cap on the device chip is sealed using a gasket having treaded surface for improved adhesion, cold weld deformation of gold, and decreased susceptibility to foreign particles resulting in a superior seal.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: December 28, 2004
    Assignee: Agilent Technologies, Inc
    Inventor: Frank S. Geefay
  • Publication number: 20040198040
    Abstract: A sloped via contact is used to connect a contact on the front side of a wafer to a contact on the back side of the wafer. The walls of a small (less than 50-80 microns wide) via have typically been difficult to coat with metal. The present invention forms a small via with sloped walls, allowing easy access to the inside walls of the via for metal sputtering or plating. The small via can be formed using a dry etch process such as the well-known deep reactive ion etching (DRIE) process. Using any isotropic plasma etch process, the walls of the via are further etched from the wafer backside to create sloped walls in the via. The via is then coated with metal to make it conductive.
    Type: Application
    Filed: April 15, 2004
    Publication date: October 7, 2004
    Inventors: Frank S. Geefay, Qing Gan
  • Patent number: 6787897
    Abstract: A gasket encloses a hermetically sealed environment between a cap wafer and a base wafer. The gasket is bonded to the base wafer using bonding material. The bonding material can be one or more of many substances that exhibit acceptable adhesion, sealing, and other properties that ensure a hermetically sealed environment. The gasket is carved out from the cap wafer material itself. The cap wafer is typically made of extremely strong and rigid material such as silicon. Since the gasket is made from the cap wafer, the gasket itself is also extremely strong and rigid.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: September 7, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Frank S Geefay, Qing Gan, Ann Mattos, Domingo A Figueredo
  • Patent number: 6777267
    Abstract: A method for separating dies on a wafer includes etching channels around the dies on a first side of the wafer, mounting the first side of the wafer to a quartz plate with an UV adhesive, and grinding a second side of the wafer until the channels are exposed on the second side of the wafer. At this point, the dies are separated but held together by the UV adhesive on the quartz plate. The method further includes mounting a second side of the wafer to a tack tape, exposing UV radiation through the quartz plate to the UV adhesive. At this point, the UV adhesive looses its adhesion so the dies are held together by the tack tape. The method further includes dismounting the quartz plate from the first side of the wafer and picking up the individual dies from the tack tape.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: August 17, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Richard C. Ruby, Frank S. Geefay, Cheol Hyun Han, Qing Gan, Andrew T. Barfknecht
  • Patent number: 6777263
    Abstract: A method for forming a wafer package includes forming a die structure, wherein the die structure includes a first wafer, a device mounted on the first wafer, a second wafer mounted atop the first wafer with a first seal ring around the device and a second seal ring around a via contact. The method further includes forming a trench in the second wafer around the first seal ring, filling the trench and the via contact with a sealing agent, patterning a topside of the second wafer to removed the excessive sealing agent and to expose a contact pad of the via contact, and singulating a die around the first seal ring.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: August 17, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Qing Gan, Richard C. Ruby, Frank S. Geefay, Andrew T. Barfknecht
  • Patent number: 6763702
    Abstract: A method and apparatus for determining the hermeticity of a semiconductor package is disclosed. Gas is introduced into the semiconductor package during packaging. Vacuum suction is then applied to the package. If the package has any leaks, the gas within will escape. The package is next scanned using a spectrometer. If the spectrometer does not detect any gas within the package cavity, the package is not hermetically sealed. In an alternate embodiment, the device is packaged first, and then immersed in a pressurized liquid. If the package has a leak, the pressure on the liquid will force liquid into the package cavity. The cavity of a properly sealed package will remain empty and dry. The package is scanned using a spectrometer. If the spectrometer detects liquid within the package, the package is not hermetically sealed.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: July 20, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Allen Chien, Frank S Geefay, Cheol Hyun Han, Qing Gan
  • Publication number: 20040118187
    Abstract: A method and apparatus for determining the hermeticity of a semiconductor package is disclosed. Gas is introduced into the semiconductor package during packaging. Vacuum suction is then applied to the package. If the package has any leaks, the gas within will escape. The package is next scanned using a spectrometer. If the spectrometer does not detect any gas within the package cavity, the package is not hermetically sealed. In an alternate embodiment, the device is packaged first, and then immersed in a pressurized liquid. If the package has a leak, the pressure on the liquid will force liquid into the package cavity. The cavity of a properly sealed package will remain empty and dry. The package is scanned using a spectrometer. If the spectrometer detects liquid within the package, the package is not hermetically sealed.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventors: Allen Chien, Frank S. Geefay, Cheol Hyun Han, Qing Gan
  • Publication number: 20040087059
    Abstract: A method for separating dies on a wafer includes etching channels around the dies on a first side of the wafer, mounting the first side of the wafer to a quartz plate with an UV adhesive, and grinding a second side of the wafer until the channels are exposed on the second side of the wafer. At this point, the dies are separated but held together by the UV adhesive on the quartz plate. The method further includes mounting a second side of the wafer to a tack tape, exposing UV radiation through the quartz plate to the UV adhesive. At this point, the UV adhesive looses its adhesion so the dies are held together by the tack tape. The method further includes dismounting the quartz plate from the first side of the wafer and picking up the individual dies from the tack tape.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 6, 2004
    Inventors: Richard C. Ruby, Frank S. Geefay, Cheol Hyun Han, Qing Gan, Andrew T. Barfknecht
  • Publication number: 20040077126
    Abstract: An apparatus includes a device chip having circuit elements fabricated on a substrate and a cap covering at least a portion of the device chip including the circuit elements such as thin film resonators. The placement of the cap on the device chip is sealed using a gasket having treaded surface for improved adhesion, cold weld deformation of gold, and decreased susceptibility to foreign particles resulting in a superior seal.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 22, 2004
    Inventor: Frank S. Geefay
  • Publication number: 20040077127
    Abstract: An apparatus includes a device chip having circuit elements fabricated on a substrate and a cap covering at least a portion of the device chip including the circuit elements such as thin film resonators. The placement of the cap on the device chip is sealed using a gasket having treaded surface for improved adhesion, cold weld deformation of gold, and decreased susceptibility to foreign particles resulting in a superior seal.
    Type: Application
    Filed: August 20, 2003
    Publication date: April 22, 2004
    Inventor: Frank S. Geefay