Patents by Inventor Frank Sai-Keung Lee
Frank Sai-Keung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923341Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: GrantFiled: September 3, 2021Date of Patent: March 5, 2024Assignee: SUNRISE MEMORY CORPORATIONInventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Patent number: 11823760Abstract: A memory system includes: (a) a memory array including numerous quasi-volatile (“QV”) memory units each configured to store a first portion of a code word encoded using an error-detecting and error-correcting code (“ECC-encoded code word”); (b) a refresh circuit for reading and writing back the first portion of the ECC-encoded code word of a selected one of the QV memory unit; (c) a global parity evaluation circuit configured to determine a global parity of the ECC-encoded code word of the selected QV memory unit; and a memory controller configured for controlling operations carried out in the memory array, wherein when the global parity of the ECC-encoded code word of the selected QV memory unit is determined at the global parity evaluation circuit to be a predetermined parity, the memory controller (i) performs error correction on the selected ECC-encoded code word and (ii) causes the first portion of the corrected ECC-encoded code word to be written back to the selected QV memory unit, instead of the refreType: GrantFiled: October 27, 2021Date of Patent: November 21, 2023Assignee: SUNRISE MEMORY CORPORATIONInventor: Frank Sai-keung Lee
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Publication number: 20230260969Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Patent number: 11670620Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: GrantFiled: January 29, 2020Date of Patent: June 6, 2023Assignee: SUNRISE MEMORY CORPORATIONInventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20230131169Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Inventors: Robert D. Norman, Eli Harari, Khandker Nazrul Quader, Frank Sai-keung Lee, Richard S. Chernicoff, Youn Cheul Kim, Mehrdad Mofidi
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Patent number: 11580038Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.Type: GrantFiled: February 5, 2021Date of Patent: February 14, 2023Assignee: SUNRISE MEMORY CORPORATIONInventors: Robert D. Norman, Eli Harari, Khandker Nazrul Quader, Frank Sai-keung Lee, Richard S. Chernicoff, Youn Cheul Kim, Mehrdad Mofidi
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Publication number: 20220148670Abstract: A memory system includes: (a) a memory array including numerous quasi-volatile (“QV”) memory units each configured to store a first portion of a code word encoded using an error-detecting and error-correcting code (“ECC-encoded code word”); (b) a refresh circuit for reading and writing back the first portion of the ECC-encoded code word of a selected one of the QV memory unit; (c) a global parity evaluation circuit configured to determine a global parity of the ECC-encoded code word of the selected QV memory unit; and a memory controller configured for controlling operations carried out in the memory array, wherein when the global parity of the ECC-encoded code word of the selected QV memory unit is determined at the global parity evaluation circuit to be a predetermined parity, the memory controller (i) performs error correction on the selected ECC-encoded code word and (ii) causes the first portion of the corrected ECC-encoded code word to be written back to the selected QV memory unit, instead of the refreType: ApplicationFiled: October 27, 2021Publication date: May 12, 2022Inventor: Frank Sai-keung Lee
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Publication number: 20210398949Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: ApplicationFiled: September 3, 2021Publication date: December 23, 2021Inventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20210248094Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.Type: ApplicationFiled: February 5, 2021Publication date: August 12, 2021Inventors: Robert D. Norman, Eli Harari, Khandker Nazrul Quader, Frank Sai-keung Lee, Richard S. Chernicoff, Youn Cheul Kim, Mehrdad Mofidi
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Publication number: 20200243486Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: ApplicationFiled: January 29, 2020Publication date: July 30, 2020Applicant: Sunrise Memory CorporationInventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Patent number: 7171525Abstract: A system including a multi-port storage device (e.g., a disk drive) and at least two users, each user coupled to a port of the storage device by a serial link. The storage device has an operational portion and an interface (including arbitration circuitry) between its ports and the operational portion. In response to a set of competing priority bids from the users, the arbitration circuitry grants one bid (including by sending an acknowledgement to the successful bidder) and preferably holds each non-granted competing bid without sending any notification to the unsuccessful bidder until the successful bidder sends a deselect signal. The system can be a RAID system including at least two disk drives and at least two controllers, where at least one drive is a multi-port device shared by at least two of the controllers. Preferably, each priority bid and deselect signal is a primitive code (e.g., an ordered sequence of a 10-bit control character and three 10-bit data characters in SATA format).Type: GrantFiled: July 31, 2002Date of Patent: January 30, 2007Assignee: Silicon Image, Inc.Inventors: Robert D. Norman, Frank Sai-Keung Lee