Abstract: A single semiconductor chip containing both I/O bus controller and DRAM controller functions. A single pin on the chip is used to provide both a zero wait state input to the I/O bus controller and to provide a local bus access (LBA) signal for inhibiting both the I/O bus controller and the DRAM controller when an external device is doing an I/O or memory operation on the local bus. Logic isprovided to produce an inhibit signal to the I/O bus controller in response to the LBA signal. Another logic circuit is provided to inhibit the DRAM controller in response to the LBA signal only when there is a memory cycle signal from the microprocessor. The use of the single pin is possible since the zero wait state isgnal will only appear during the latter part of an I/O or memory cycle, which is mutually exclusive with the start of an I/O or memory cycle, which is the only time the LBA signal will appear.