Patents by Inventor Frank Szu-Jen Yang
Frank Szu-Jen Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11029749Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). At least one of the ASICs is configured to process incoming data packets and outgoing data packets. At least one of the ASICs is configured to move data between a respective networking module and a destination networking module. The system also includes a cable backplane having a number of parallel cables configured to transmit data between the number of ASICs.Type: GrantFiled: March 31, 2017Date of Patent: June 8, 2021Assignee: Platina Systems Corp.Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Mark Tehmin Yin
-
Patent number: 10956832Abstract: A method is provided to produce training data set for training an inference engine to predict events in a data center comprising: producing probe vectors corresponding to components of a data center, each probe vector including a sequence of data elements, one of the probe vectors indicating an event at a component and at a time of the event; and producing at a master device a set of training snapshots, wherein each training snapshot includes a subsequence of data elements that corresponds to a time increment that matches or that occurred not later than the indicated time of occurrence of the event.Type: GrantFiled: June 22, 2018Date of Patent: March 23, 2021Assignee: Platina Systems CorporationInventors: Frank Szu-Jen Yang, Ramanagopal V. Vogety, Sharad Mehrotra
-
Publication number: 20190392354Abstract: A method is provided to produce training data set for training an inference engine to predict events in a data center comprising: producing probe vectors corresponding to components of a data center, each probe vector including a sequence of data elements, one of the probe vectors indicating an event at a component and at a time of the event; and producing at a master device a set of training snapshots, wherein each training snapshot includes a subsequence of data elements that corresponds to a time increment that matches or that occurred not later than the indicated time of occurrence of the event.Type: ApplicationFiled: June 22, 2018Publication date: December 26, 2019Inventors: Frank Szu-Jen Yang, Ramanagopal V. Vogety, Sharad Mehrotra
-
Patent number: 10416752Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.Type: GrantFiled: October 22, 2018Date of Patent: September 17, 2019Assignee: Platina Systems CorporationInventors: Frank Szu-Jen Yang, Jason Luo Pang, Eliot Michael Dresselhaus, Dino Farinacci, Andreas Demetrios Bovopoulos, Mark Tehmin Yin
-
Patent number: 10386913Abstract: In one embodiment, a system includes a number of networking modules. Each module includes a respective voltage controller and a voltage-configuration circuit. The voltage-configuration circuit includes a number of transistors that are each coupled to a respective resistor. The system also includes one or more processors coupled to the voltage controllers including instructions executable by the processors. The processors being operable when executing the instructions to configure, for each module, an on-state or off-state of the transistors coupled to the respective resistor. The transistors coupled to the respective resistor correspond to a bit of a number of under-voltage thresholds. The processors are also operable to preset, during a module initialization, a relative ranking of under-voltage shutdown between the modules by setting the transistors. At least one of the number of networking modules has a different under-voltage threshold level relative to another one of the networking modules.Type: GrantFiled: March 31, 2017Date of Patent: August 20, 2019Assignee: Platina Systems CorporationInventors: Frank Szu-Jen Yang, Jason Luo Pang
-
Publication number: 20190056776Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Eliot Michael Dresselhaus, Dino Farinacci, Andreas Demetrios Bovopoulos, Mark Tehmin Yin
-
Patent number: 10139894Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.Type: GrantFiled: March 31, 2017Date of Patent: November 27, 2018Assignee: Platina Systems Corp.Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Eliot Michael Dresselhaus, Dino Farinacci, Andreas Demetrios Bovopoulos, Mark Tehmin Yin
-
Publication number: 20170289029Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.Type: ApplicationFiled: March 31, 2017Publication date: October 5, 2017Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Thomas M. Grennan, Eliot Michael Dresselhaus, Dino Farinacci, Andreas Demetrios Bovopoulos, Mark Tehmin Yin
-
Publication number: 20170286339Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). At least one of the ASICs is configured to process incoming data packets and outgoing data packets. At least one of the ASICs is configured to move data between a respective networking module and a destination networking module. The system also includes a cable backplane having a number of parallel cables configured to transmit data between the number of ASICs.Type: ApplicationFiled: March 31, 2017Publication date: October 5, 2017Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Mark Tehmin Yin
-
Publication number: 20170285729Abstract: In one embodiment, a system includes a number of networking modules. Each module includes a respective voltage controller and a voltage-configuration circuit. The voltage-configuration circuit includes a number of transistors that are each coupled to a respective resistor. The system also includes one or more processors coupled to the voltage controllers including instructions executable by the processors. The processors being operable when executing the instructions to configure, for each module, an on-state or off-state of the transistors coupled to the respective resistor. The transistors coupled to the respective resistor correspond to a bit of a number of under-voltage thresholds. The processors are also operable to preset, during a module initialization, a relative ranking of under-voltage shutdown between the modules by setting the transistors. At least one of the number of networking modules has a different under-voltage threshold level relative to another one of the networking modules.Type: ApplicationFiled: March 31, 2017Publication date: October 5, 2017Inventors: Frank Szu-Jen Yang, Jason Luo Pang