Abstract: As indicated above, the present approach provides an automated communication method and system for concurrently responding to a plurality of events using multiple rules with multiple messaging (notification) timelines (patterns) per event, operating under the constraint of each respective event's dynamic duration or lifespan while considering the state of the event (example: active, paused, inactive). Each individual rule may be configured to govern how messaging agents react with respect to event severities, multiple days and hours of operation of the rule, changes to monitored data points, and multiple messaging (notification) timelines (patterns) with respect to the duration of an event. The multiple messaging timelines (patterns) may differ with respect to how (messaging protocols used and message content/profiles) and to whom messages are sent within multiple varying fragments of time (also referred to herein as escalation levels) encapsulated within the duration or lifespan of an event.

Abstract: A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material.

Abstract: An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapsulated by a thin film of titanium nitride.