Abstract: Packaged transistor devices are provided that include a transistor on a base of the packaged transistor device, the transistor comprising a control terminal and an output terminal, a first bond wire electrically coupled between an input lead and the control terminal of the transistor, a second bond wire electrically coupled between an output lead and the output terminal of the transistor, and an isolation material that is and physically between the first bond wire and the second bond wire, wherein the isolation material is configured to reduce a coupling between the first bond wire and the second bond wire.

Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.

Abstract: A transistor device includes a semiconductor structure, a plurality of gate fingers extending on the semiconductor structure in a first direction, a plurality of gate interconnects that each have a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a respective gate finger by a plurality of first conductive vias, and a plurality of gate runners extending on the semiconductor structure in the first direction. At least one gate interconnect of the gate interconnects is connected to one of the gate runners by a second conductive via at an interior position of the at least one gate interconnect that is remote from the first end and the second end of the at least one gate interconnect.

Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.

Abstract: Packaged transistor devices are provided that include a transistor on a base of the packaged transistor device, the transistor comprising a control terminal and an output terminal, a first bond wire electrically coupled between an input lead and the control terminal of the transistor, a second bond wire electrically coupled between an output lead and the output terminal of the transistor, and an isolation material that is and physically between the first bond wire and the second bond wire, wherein the isolation material is configured to reduce a coupling between the first bond wire and the second bond wire.

Abstract: A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.

Abstract: A phase shifter having a four port hybrid coupler is provided. The four port hybrid coupler has first and second input ports and first and second output ports. The four port hybrid coupler is configured to shift the phase of an RF signal as between the first and second input ports. First and second active semiconductor devices are connected to first and second output ports. The first and second active semiconductor devices are configured to change the phase shift of the RF signal as between the first and second input ports based upon a varying voltage.

Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.

Abstract: A multi-cell transistor includes a semiconductor structure and a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor including a gate finger that extends in a first direction on the semiconductor structure. The gate fingers are spaced apart from each other along a second direction and arranged on the semiconductor structure in a plurality of groups. A first distance in the second direction between adjacent gate fingers in a first of the groups is less than a second distance in the second direction between a first gate finger that is at one end of the first group and a second gate finger that is in a second of the groups, where the second gate finger is adjacent the first gate finger.

Abstract: A transistor device includes a semiconductor structure, a plurality of gate fingers extending on the semiconductor structure in a first direction, a plurality of gate interconnects that each have a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a respective gate finger by a plurality of first conductive vias, and a plurality of gate runners extending on the semiconductor structure in the first direction. At least one gate interconnect of the gate interconnects is connected to one of the gate runners by a second conductive via at an interior position of the at least one gate interconnect that is remote from the first end and the second end of the at least one gate interconnect.

Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.

Abstract: A multi-cell transistor includes a semiconductor structure and a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor including a gate finger that extends in a first direction on the semiconductor structure. The gate fingers are spaced apart from each other along a second direction and arranged on the semiconductor structure in a plurality of groups.

Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.

Abstract: A transistor device includes a semiconductor structure, a plurality of gate fingers extending on the semiconductor structure in a first direction, a plurality of gate interconnects that each have a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a respective gate finger by a plurality of first conductive vias, and a plurality of gate runners extending on the semiconductor structure in the first direction. At least one gate interconnect of the gate interconnects is connected to one of the gate runners by a second conductive via at an interior position of the at least one gate interconnect that is remote from the first end and the second end of the at least one gate interconnect.

Abstract: An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.

Abstract: An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.

Abstract: An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.

Abstract: An amplifier circuit includes a first port, a second port, a reference potential port, and an RF amplifier device having a first terminal electrically coupled to the first port, a second terminal electrically coupled to the second port, and a reference potential terminal electrically coupled to the reference potential port. The RF amplifier device amplifies an RF signal across an RF frequency range that includes a fundamental RF frequency. An impedance matching network is electrically coupled to the first terminal and the first port. The impedance matching network includes a baseband termination circuit that presents low impedance in a baseband frequency region, a fundamental frequency matching circuit that presents a complex conjugate of an intrinsic impedance of the RF amplifier device in the RF frequency range, and a second order harmonic termination circuit that presents low impedance at second order harmonics of frequencies in the fundamental RF frequency range.

Abstract: A phase shifter having a four port hybrid coupler is provided. The four port hybrid coupler has first and second input ports and first and second output ports. The four port hybrid coupler is configured to shift the phase of an RF signal as between the first and second input ports. First and second active semiconductor devices are connected to first and second output ports.

Abstract: An RF package includes a metal flange, an RF input lead, an RF output lead, and an electrically conductive die attach area. An RF transistor that is configured to amplify an RF signal is mounted in the die attach area. The RF transistor includes an input terminal that is electrically coupled to the RF input lead, an output terminal that is electrically coupled to the RF output lead, and a reference potential terminal that is electrically connected to the die attach area. A first capacitor having one or more upper metal plates, and a dielectric region is mounted in the die attach area and is electrically coupled to the RF transmission path of the RF signal. The first capacitor is configured to simultaneously match an impedance of the RF transistor at a fundamental frequency of the RF signal and to filter a higher order harmonic of the fundamental frequency.