Patents by Inventor Frank V. Liucci

Frank V. Liucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6339022
    Abstract: A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: January 15, 2002
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Edward C. Cooney, III, George A. Dunbar, III, Cheryl G. Faltermeier, Jeffrey D. Gilbert, Ronald D. Goldblatt, Nancy A. Greco, Stephen E. Greco, Frank V. Liucci, Glenn Robert Miller, Bruce A. Root, Andrew H. Simon, Anthony K. Stamper, Ronald A. Warren, David H. Yao
  • Patent number: 6159870
    Abstract: A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480.degree. C. at sub-atmospheric pressures of about 200 Torr. Preferably, gaseous reactants used in the method comprise TEOS, FTES, TEPO and TEB with an ozone/oxygen mixture. Dopant concentrations of boron and phosphorus are sufficiently low such that surface crystallite defects and hygroscopicity are avoided. The as-deposited films at lower aspect ratio gaps are substantially void-free such that subsequent anneal of the film is not required. Films deposited into higher aspect ratio gaps are annealed at or below about 750.degree. C., well within the thermal budget for most DRAM, logic and merged logic-DRAM chips. The resultant FBPSG layer contains less than or equal to about 5.0 wt % boron, less than about 4.0 wt % phosphorus, and about 0.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: December 12, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Richard A. Conti, Frank V. Liucci, Darryl D. Restaino
  • Patent number: 6077786
    Abstract: Filling of narrow and/or high aspect ratio gaps and trenches with silicate glass is accomplished at reduced temperatures and without reflow by etching the glass concurrently with thermal chemical vapor deposition of the glass such that the deposition rate will exceed the etching rate by a relatively small net deposition rate near the surface with the excess deposition rate increasing over the depth of the trench or gap. The as-deposited glass film is made dense and stable by carrying out the concurrent etch and deposition process at an elevated temperature but which is within the maximum temperature and heat budget which can be tolerated by structures formed by previously performed processes. Fluorine can be incorporated in the silicate glass film as a dopant in sufficient concentration to reduce dielectric constant of the film. Phosphorus and/or boron can be incorporated into the film, as well, and may enhance void-free filling of trenches and gaps.
    Type: Grant
    Filed: May 8, 1997
    Date of Patent: June 20, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Richard A. Conti, Donna R. Cote, Frank V. Liucci, Son V. Nguyen