Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention.

Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: A golf appliance, such as a glove and golf club grip system providing for club specific parametric signal transfer there between providing for the ability to automatically score golf rounds and analyze golf club swings in real-time. In addition, enhanced capability may also be achieved by integrating GPS parametric and golf course specific information. One aspect of the invention includes the capability to provide power between the golf glove and a golf club grip. Another aspect of the invention transfers data particular to a player's swing, a ball strike, and club information.

Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention.

Abstract: A bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is coupled between the second bus and the link.

Abstract: A methodology by which a host computer can dynamically rebalance PCI-to-PCI bridges to overcome Operating System/BIOS and Chipset limitations in order to allow multiple level PCI buses. This methodology also allows hot-swappable PCI buses to be added and removed without failure. Additionally this method allows for proper I/O resource allocation where previously alliasing preventing this. The present invention overcomes the limitations of an Operating System, such as Windows 2000 and Windows XP, to allow a PCI bus segment to be added by rebalancing the PCI bus tree and resource requirements as needed in order to fit the new PCI bus segment.

Abstract: A bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is coupled between the second bus and the link.

Abstract: An improved extended cardbus/PC card controller (20) incorporating proprietary Split-Bridge™ high speed serial communication technology for interconnecting a conventional parallel system bus via a high speed serial link with a remote peripheral device. The extend cardbus/PC card controller is adapted to interface the parallel system bus, which may be PCI, PCMCIA, integrated, or some other parallel I/O bus architecture, with peripheral devices via PC cards, and now optionally via a high speed serial link using the proprietary serial Split-Bridge™ technology. The serial Split-Bridge™ technology provides real time interconnection between the parallel system bus and the remote device which may also be based on a parallel system data bus architecture, over a serial link, which serial link appears to be transparent between the buses and thus facilitates high speed data transfer exceeding data rates of 1.0 GigaHertz.

Abstract: A bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link.

Abstract: A methodology by which a host computer can dynamically rebalance PCI-to-PCI bridges to overcome Operating System/BIOS and Chipset limitations in order to allow multiple level PCI buses. This methodology also allows hot-swappable PCI buses to be added and removed without failure. Additionally this method allows for proper I/O resource allocation where previously alliasing preventing this. The present invention overcomes the limitations of an Operating System, such as Windows 2000 and Windows XP, to allow a PCI bus segment to be added by rebalancing the PCI bus tree and resource requirements as needed in order to fit the new PCI bus segment.

Abstract: A bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is coupled between the second bus and the link.

Abstract: An improved extended cardbus/PC card controller (20) incorporating proprietary Split-Bridge™ high speed serial communication technology for interconnecting a conventional parallel system bus via a high speed serial link with a remote peripheral device. The extend cardbus/PC card controller is adapted to interface the parallel system bus, which may be PCI, PCMCIA, integrated, or some other parallel I/O bus architecture, with peripheral devices via PC cards, and now optionally via a high speed serial link using the proprietary serial Split-Bridge™ technology. The serial Split-Bridge™ technology provides real time interconnection between the parallel system bus and the remote device which may also be based on a parallel system data bus architecture, over a serial link, which serial link appears to be transparent between the buses and thus facilitates high speed data transfer exceeding data rates of 1.0 GigaHertz.