Abstract: A back biasing technique is provided for increasing the field inversion voltage between adjacent MOS transistors and for reducing parasitic capacitances in an integrated circuit. The use of a charge pump is avoided by connecting the body portions of the MOS transistors to ground and the sources of the MOS transistors to the anode of a diode, the cathode of which are connected to a reference voltage such as to ground. In this manner, the sources are back biased relative to the material in which they are formed by a diode forward voltage drop. This technique is particularly applicable to CMOS circuits operating from a 3.3 volt supply, with p-well doping densities in excess of 1.times.10.sup.17 atoms/cm.sup.3.

Abstract: A TTL to CMOS buffer circuit includes a relatively high-speed first inverter path and a second relatively low-speed inverter path connected to the first path and effective to control the operation of the first path inverter so that short-duration positive- or negative-going noise pulses of amplitude up to 2.4 volts do not incorrectly affect the output level.

Abstract: A static RAM cell includes a first pair of transistors, which act as pass or switching transistors during a read or write operation, and as loads during a refresh operation, and a second pair of current sink transistors connected as a cross-coupled flip-flop and connected to the first pair of transistors. The operation of the memory cell transistors during read and write and refresh operations is controlled by different levels of a control signal applied to their respective control terminals, whereby refreshing does not affect reading or writing of data from or into the SRAM cell.