Abstract: A circuit for an electrical load comprises a passive transformer, the secondary of which is connected to power cells for each phase according to the transformer tappings. Each power cell comprises a low cost but efficient power factor correction circuit to produce lower harmonics on the transformer.

Abstract: A voltage measurement is made between two points in a circuit. If the measured voltage exceeds a predetermined amount, a switch is operated to electrically connect the two points.

Abstract: A circuit for an electrical load comprises a passive transformer, the secondary of which is connected to power cells for each phase according to the transformer tappings. Each power cell comprises a low cost but efficient power factor correction circuit to produce lower harmonics on the transformer.

Abstract: A voltage measurement is made between two points in a circuit. If the measured voltage exceeds a predetermined amount, a switch is operated to electrically connect the two points.

Abstract: Application software and data files (21-25, 31-34) for operating systems and processors having incompatible object code format requirements may be placed on the same memory card (10). Memory card (10) may be used by any system (16, 18) receiving the physical format of memory card (10) and whose operating system can read the logical format of memory card (10). At least one card configuration file (40) having a preselected name unique to each operating system having different object code format requirements is stored on memory card (10). Card configuration file (40) includes the names and location information for only application software and data files (21-25, 31-34) accessible and executable by that operating system. Consequently, each operating system recognizes only that application software and data files having compatible object code format requirements.

Abstract: A system for processing a bit map of pixel data signals representative of a multi-dimensional array of imagery data (e g. alpha-numeric text) for transmission over a facsimile communication channel are compressed by providing a plurality of data compression units, a respective one of which is capable of compressing data supplied to it at a compression rate that is only a fraction of the data rate. The bit map is subsampled by demultiplexing the bit map into sub-arrays of data. The sub-array data is coupled to respective sets of compression units, which executes parallel, two-dimensional compression of the demultiplexed sub-array data.

Abstract: A circuit for interfacing (parallel format) TTL signals with a serial format ECL signal port includes a parallel-to-serial shift register, a first voltage level shifting stage and an output, TTL-ECL level shifting stage, connected in cascade. Each of the shift register and the first level shifting stage is powered exclusively by an on-board TTL power supply. The output level shifting stage is powered by the on-board TTL supply and from an external connection to a downstream module. The serial output of the shift register is a `positive ECL` signal having a voltage swing corresponding to that of conventional negative polarity ECL signals. From this signal the first level shifting stage produces an intermediate level (quasi analog) signal which transitions between reduced or intermediate high and low voltage levels about a switching leel corresponding to that (e.g. +1.5 volts) of normal TTL signals but having the ELC-type voltage swing.