Patents by Inventor Frank Y. Lin
Frank Y. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220108875Abstract: A gas delivery system configured to provide deposition and etch gases to a processing chamber for a rapid alternating process includes a first valve arranged to provide deposition gas from a deposition gas manifold to a first zone of a gas distribution device via a first orifice and provide the deposition gas from the deposition gas manifold to a second zone of the gas distribution device via a second orifice having a diameters than the first orifice. A second valve is arranged to provide etch gas from the etch gas manifold to the first zone of the gas distribution device via a third orifice and provide the etch gas from the etch gas manifold to the second zone of the gas distribution device via a fourth orifice having a different diameter than the third orifice.Type: ApplicationFiled: January 23, 2020Publication date: April 7, 2022Inventors: William THIE, Jisoo KIM, Alan J. MILLER, Lai WEl, Frank Y. LIN, Jun Hee Hee HAN, Jie LIU, Conan CHlANG, Michael John MARTIN, Nicholas John CELESTE
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Patent number: 8871105Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.Type: GrantFiled: March 9, 2012Date of Patent: October 28, 2014Assignee: Lam Research CorporationInventors: Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller, Qing Xu, Seongjun Heo, Jin Hwan Ham, Sang Joon Yoon, Camelia Rusu
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Patent number: 8668805Abstract: A semiconductor device may be formed by the method comprising providing a patterned photoresist mask over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end, placing a coating over the at least one photoresist line comprising at least one cycle, wherein each cycle comprises: a) depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and b) hardening the polymer layer, and etching features into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.Type: GrantFiled: June 30, 2008Date of Patent: March 11, 2014Assignee: Lam Research CorporationInventors: Gowri Kota, Frank Y. Lin, Qinghua Zhong
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Patent number: 8609548Abstract: A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.Type: GrantFiled: July 21, 2011Date of Patent: December 17, 2013Assignee: Lam Research CorporationInventors: Qing Xu, Camelia Rusu, Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller
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Publication number: 20130237062Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Inventors: Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller, Qing Xu, Seongjun Heo, Jin Hwan Ham, Sang Joon Yoon, Camelia Rusu
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Patent number: 8480913Abstract: The amount of RF power supplied to a plasma in a vacuum plasma processing chamber is gradually changed on a preprogrammed basis in response to signals stored in a computer memory. The computer memory stores signals so that other processing chamber parameters (pressure, gas species and gas flow rates) remain constant while the gradual change occurs. The stored signals enable rounded corners, instead of sharp edges, to be etched, e.g., at an intersection of a trench wall and base.Type: GrantFiled: June 30, 2011Date of Patent: July 9, 2013Assignee: Lam Research CorporationInventors: Tuqiang Ni, Weinan Jiang, Frank Y. Lin, Chung-Ho Huang
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Publication number: 20120309194Abstract: A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.Type: ApplicationFiled: July 21, 2011Publication date: December 6, 2012Applicant: LAM RESEARCH CORPORATIONInventors: Qing Xu, Camelia Rusu, Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller
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Publication number: 20110253673Abstract: The amount of RF power supplied to a plasma in a vacuum plasma processing chamber is gradually changed on a preprogrammed basis in response to signals stored in a computer memory. The computer memory stores signals so that other processing chamber parameters (pressure, gas species and gas flow rates) remain constant while the gradual change occurs. The stored signals enable rounded corners, instead of sharp edges, to be etched, e.g., at an intersection of a trench wall and base.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: LAM RESEARCH CORPORATIONInventors: Tuqiang NI, Frank Y. Lin, Chung-Ho Huang, Weinan Jiang
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Patent number: 7491343Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is provided over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end is provided. A polymer layer is placed over the at least one photoresist line, wherein a thickness of the polymer layer at the line end of the photoresist line is greater than a thickness of the polymer layer on the sidewalls of the photoresist line. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) ratio is less than or equal to 1.Type: GrantFiled: January 10, 2007Date of Patent: February 17, 2009Assignee: Lam Research CorporationInventors: Yoko Yamaguchi Adams, Gowri Kota, Frank Y. Lin, Qinghua Zhong
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Publication number: 20080268211Abstract: A semiconductor device may be formed by the method comprising providing a patterned photoresist mask over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end, placing a coating over the at least one photoresist line comprising at least one cycle, wherein each cycle comprises: a) depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and b) hardening the polymer layer, and etching features into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.Type: ApplicationFiled: June 30, 2008Publication date: October 30, 2008Applicant: LAM RESEARCH CORPORATIONInventors: Gowri KOTA, Frank Y. LIN, Qinghua ZHONG
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Patent number: 7407597Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with at least one photoresist line having a pair of sidewalls ending at a line end. A coating is placed over the photoresist line comprising at least one cycle of depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and hardening the polymer layer. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.Type: GrantFiled: September 14, 2006Date of Patent: August 5, 2008Assignee: LAM Research CorporationInventors: Gowri Kota, Frank Y. Lin, Qinghua Zhong
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Publication number: 20080087637Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with at least one photoresist line having a pair of sidewalls ending at a line end. A coating is placed over the photoresist line comprising at least one cycle of depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and hardening the polymer layer. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.Type: ApplicationFiled: September 14, 2006Publication date: April 17, 2008Applicant: LAM Research CorporationInventors: Gowri Kota, Frank Y. Lin, Qinghua Zhong
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Patent number: 6897156Abstract: 200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.Type: GrantFiled: January 21, 2003Date of Patent: May 24, 2005Assignee: Lam Research CorporationInventors: Tuqiang Ni, Kenji Takeshita, Tom Choi, Frank Y. Lin
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Patent number: 6617257Abstract: A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O2-free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defined by the photoresist. The etchant gas can include SO2 and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.Type: GrantFiled: March 30, 2001Date of Patent: September 9, 2003Assignee: Lam Research CorporationInventors: Tuqiang Ni, Weinan Jiang, Conan Chiang, Frank Y. Lin, Chris Lee, Dai N. Lee
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Publication number: 20030106645Abstract: 200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.Type: ApplicationFiled: January 21, 2003Publication date: June 12, 2003Applicant: LAM RESEARCH CORPORATIONInventors: Tuqiang Ni, Kenji Takeshita, Tom Choi, Frank Y. Lin
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Patent number: 6531029Abstract: 200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic; fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.Type: GrantFiled: June 30, 2000Date of Patent: March 11, 2003Assignee: Lam Research CorporationInventors: Tuqiang Ni, Kenji Takeshita, Tom Choi, Frank Y. Lin
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Patent number: 6514378Abstract: An apparatus and method for consecutively processing a series of semiconductor substrates with minimal plasma etch rate variation following cleaning with fluorine-containing gas and/or seasoning of the plasma etch chamber. The method includes steps of (a) placing a semiconductor substrate on a substrate support in a plasma etching chamber, (b) maintaining a vacuum in the chamber, (c) etching an exposed surface of the substrate by supplying an etching gas to the chamber and energizing the etching gas to form a plasma in the chamber, (d) removing the substrate from the chamber; and (e) consecutively etching additional substrates in the chamber by repeating steps (a-d), the etching step being carried out by minimizing a recombination rate of H and Br on a silicon carbide edge ring surrounding the substrate at a rate sufficient to offset a rate at which Br is consumed across the substrate. The method can be carried out using pure HBr or combination of HBr with other gases.Type: GrantFiled: March 31, 2000Date of Patent: February 4, 2003Assignee: Lam Research CorporationInventors: Tuqiang Ni, Kenji Takeshita, Tom Choi, Frank Y. Lin, Wenli Collison
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Publication number: 20020182881Abstract: A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O2-free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defmed by the photoresist. The etchant gas can include SO2 and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.Type: ApplicationFiled: March 30, 2001Publication date: December 5, 2002Inventors: Tuqiang Ni, Weinan Jiang, Conan Chiang, Frank Y. Lin, Chris Lee, Dai N. Lee
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Publication number: 20020139477Abstract: The amount of RF power supplied to a plasma in a vacuum plasma processing chamber is gradually changed on a preprogrammed basis in response to signals stored in a computer memory. The computer memory stores signals so that other processing chamber parameters (pressure, gas species and gas flow rates) remain constant while the gradual change occurs. The stored signals enable rounded corners, instead of sharp edges, to be etched, e.g., at an intersection of a trench wall and base.Type: ApplicationFiled: March 30, 2001Publication date: October 3, 2002Applicant: Lam Research CorporationInventors: Tuqiang Ni, Frank Y. Lin, Chung-Ho Huang, Weinan Jiang