Patents by Inventor Frank Yu

Frank Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220376719
    Abstract: Systems, devices, and methods related to using model architecture search for hardware configuration are provided. A method includes receiving, by a computer-implemented system, information associated with a pool of processing units; receiving, by the computer-implemented system, a data set associated with a data transformation operation; training, based on the data set and the information associated with the pool of processing units, a parameterized model associated with the data transformation operation, where the training includes updating at least one parameter of the parameterized model associated with configuring at least a subset of the processing units in the pool; and outputting, based on the training, one or more configurations for at least the subset of the processing units in the pool.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 24, 2022
    Applicant: Analog Devices, Inc.
    Inventors: Tao YU, Cristobal ALESSANDRI, Frank YAUL, Wenjie LU, Shyam Chandrasekhar NAMBIAR
  • Publication number: 20220376659
    Abstract: Systems, devices, and methods related to using model architecture search for hardware configuration are provided. An example apparatus includes an input node to receive an input signal; a pool of processing units to perform one or more arithmetic operations and one or more signal selection operations, wherein each of the processing units in the pool is associated with at least one parameterized model corresponding to a data transformation operation; and a control block to configure, based on a first parameterized model, a first subset of the processing units in the pool, where the first subset of the processing units processes the input signal to generate a first signal.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 24, 2022
    Applicant: Analog Devices, Inc.
    Inventors: Tao YU, Cristobal ALESSANDRI, Frank YAUL, Wenjie LU, Shyam Chandrasekhar NAMBIAR
  • Publication number: 20220326588
    Abstract: A phase shift keying modulator. The modulator comprises: a plurality of silicon waveguides provided in a device layer of a silicon-on-insulator platform, the silicon-on-insulator platform including one or more cavities; one or more III-V semiconductor based devices located within the one or more cavities of the silicon-on-insulator platform, each III-V semiconductor-based device including a III-V semiconductor based waveguide which is coupled at an input end to one of the plurality of silicon waveguides and coupled at an output end to another of the plurality of silicon waveguides, each III-V semiconductor based waveguide comprising an active phase modulating portion; and one or more contacts in electrical contact with each active phase modulating portion, such that the phase shift keying modulator is operable to modulate the phase of an optical wave passing through each active phase modulating portion.
    Type: Application
    Filed: May 2, 2022
    Publication date: October 13, 2022
    Inventors: Guomin YU, Aaron John ZILKIE, Frank PETERS
  • Publication number: 20220317539
    Abstract: A phase shift keying modulator. The modulator comprises: a plurality of silicon waveguides provided in a device layer of a silicon-on-insulator platform, the silicon-on-insulator platform including one or more cavities; one or more III-V semiconductor based devices located within the one or more cavities of the silicon-on-insulator platform, each III-V semiconductor-based device including a III-V semiconductor based waveguide which is coupled at an input end to one of the plurality of silicon waveguides and coupled at an output end to another of the plurality of silicon waveguides, each III-V semiconductor based waveguide comprising an active phase modulating portion; and one or more contacts in electrical contact with each active phase modulating portion, such that the phase shift keying modulator is operable to modulate the phase of an optical wave passing through each active phase modulating portion.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 6, 2022
    Inventors: Guomin YU, Aaron John ZILKIE, Frank PETERS
  • Publication number: 20220281886
    Abstract: The present invention relates to Compounds of Formula I: I and pharmaceutically acceptable salts or prodrug thereof. The present invention also relates to compositions comprising at least one compound of Formula I, and methods of using the compounds of Formula I for treatment or prophylaxis of cardiometabolic diseases including high blood pressure, heart failure, kidney disease, and diabetes in a subject.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 8, 2022
    Applicant: Merck Sharp Dohme Corp.
    Inventors: Frank Bennett, Jason E. Imbriglio, Angela D. Kerekes, Tanweer Khan, Claire Lankin, Derun Li, Zhicai Wu, Yusheng Xiong, Hyewon Youm, Yang Yu, Feng Ye, Anthappan Tony Kurissery, Venukrishnan Komanduri
  • Patent number: 11406643
    Abstract: Provided herein are methods for the treatment of brain metastasis by administering a kinase inhibitor targeted to a metastasis-promoting kinase identified by an in vivo kinase screen.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 9, 2022
    Assignee: Board of Regents, The University of Texas System
    Inventors: Dihua Yu, Frank Lowery, Chenyu Zhang, Sunil Acharya, Ping Li
  • Patent number: 11379950
    Abstract: Systems and methods directed to placing content are described. More specifically, content is received and depth information corresponding to an external environment of the computing device is obtained. An indication to associate the content with a location based on the depth information is received from a user. Information for at least one plane associated with the depth information at the location is obtained and at least a portion of the content is warped to match the at least one plane based on the depth information.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: July 5, 2022
    Assignee: LEMON INC.
    Inventors: Frank Hamilton, Hwankyoo Shawn Kim, Zhixiong Lu, Qingyang Lv, WeiShan Yu, Ben Ma
  • Patent number: 11081428
    Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.
    Type: Grant
    Filed: August 10, 2019
    Date of Patent: August 3, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Stanley Chou, Yuh-Harng Chien, Steven Alfred Kummerl, Bo-Hsun Pan, Pi-Chiang Huang, Frank Yu, Chih-Chien Ho
  • Publication number: 20210043548
    Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.
    Type: Application
    Filed: August 10, 2019
    Publication date: February 11, 2021
    Applicant: Texas Instruments Incorporated
    Inventors: Stanley Chou, Yuh-Harng Chien, Steven Alfred Kummerl, Bo-Hsun Pan, Pi-Chiang Huang, Frank Yu, Chih-Chien Ho
  • Publication number: 20190294345
    Abstract: A Green NAND SSD (GNSD) controller receives reads and writes from a host and writes to flash memory. A SSD DRAM has a DRAM Translation Layer (ETL) with buffers managed by the GNSD controller. The GNSD controller performs deduplication, compression, encryption, high-level error-correction, and grouping of host data writes, and manages mapping tables to store host write data in the SSD DRAM to reduce writes to flash memory. The GNSD controller categorizes host writes as data types for paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the GNSD controller. Status bits include two overwrite bits indicating frequently-written data that is retained in the SSD DRAM rather than being flushed to flash and re-allocated.
    Type: Application
    Filed: March 21, 2018
    Publication date: September 26, 2019
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen, Yao-Tse Chang, Yan Zhou
  • Patent number: 9841911
    Abstract: A Green NAND Device (GND) driver application queries AC line and battery status and then stores an image of processor states and caches and a resume routine to DRAM when power failure occurs. A DRAM image is then stored to flash memory for a persistent mode when battery power is available. The image in DRAM may be a partial image that includes entries, flushed caches, processor contexts, ramdisks, write caches, and a resume context. Endurance of flash memory is increased by a Super Enhanced Endurance Device (SEED) SSD. In a power down mode, the GND driver limits DRAM use and only caches in DRAM data that can be deleted on power down. Host accesses to flash are intercepted by the GND driver and categorized by data type. Paging files and temporary files cached in DRAM are optionally written to flash.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: December 12, 2017
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen, Yi Syu Yan
  • Patent number: 9720616
    Abstract: A Green NAND SSD Driver (GNSD) driver executes on a host to increase data-retention of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the GNSD driver using upper and lower-level filter drivers. A retention-check timer causes a retention routine to be periodically executed. The routine sends high-level commands to the SEED that causes the SEED to refresh either all data or just data blocks with older write dates. Data is refreshed by moving to a new physical block. The retention routine can track write dates of logical blocks and command a SSD to move logical blocks with older write dates. A retention card has a controller that performs the retention routine when not connected to a host, while a SEED power card allows the SEED to refresh data when no host is attached to the SEED.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: August 1, 2017
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen
  • Patent number: 9601508
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: March 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Chan Park, Atsushi Suyama, Frank Yu, Hiroyuki Ogawa, Ryoichi Honma, Kensuke Yamaguchi, Hiroaki Iuchi, Naoki Takeguchi, Tuan Pham, Kiyohiko Sakakibara, Jiao Chen
  • Patent number: 9548108
    Abstract: A Virtual-Memory Device (VMD) driver and application execute on a host to increase endurance of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the VMD driver using upper and lower-level filter drivers and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the SSD. Ramdisks and caches for storing each data type in the host DRAM are managed and flushed to the SSD by the VMD driver. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 17, 2017
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen, Yi Syu Yan
  • Patent number: 9547589
    Abstract: A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 17, 2017
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen
  • Patent number: 9489258
    Abstract: A GNSD Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES or AES. A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an SEED SSD.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: November 8, 2016
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen, Yao-Tse Chang, Yan Zhou
  • Publication number: 20160315095
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.
    Type: Application
    Filed: October 23, 2015
    Publication date: October 27, 2016
    Inventors: Jongsun Sel, Chan Park, Atsushi Suyama, Frank Yu, Hiroyuki Ogawa, Ryoichi Honma, Kensuke Yamaguchi, Hiroaki Iuchi, Naoki Takeguchi, Tuan Pham, Kiyohiko Sakakibara, Jiao Chen
  • Publication number: 20160246807
    Abstract: A GNSD Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES or AES. A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an SEED SSD.
    Type: Application
    Filed: May 3, 2016
    Publication date: August 25, 2016
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen, Yao-Tse Chang, Yan Zhou
  • Patent number: 9405621
    Abstract: A controller for a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD) increases flash endurance using a DRAM buffer. Host accesses to flash are intercepted by the controller and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type in the DRAM before storage by lower-level flash devices such as eMMC, UFS, or iSSD. Caches in the DRAM buffer for storing each data type are managed and flushed to the flash devices by the controller. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: August 2, 2016
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen
  • Patent number: 9389952
    Abstract: A GNSD (Green NAND Solid State Drive) Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES (Data Encryption Standard) or AES (Advanced Encryption Standard). A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an (Super Enhanced Endurance Device) SEED SSD (Solid State Drive).
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 12, 2016
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen, Yao-Tse Chang, Yan Zhou