Abstract: The present disclosure concerns a method and apparatus for accessing a memory device, such as a dynamic random access memory (DRAM). The DRAM has a plurality of rows, wherein each row has a plurality of DRAM paragraphs comprised of a plurality of contiguous columns. A linear shift register (LSR) translates a plurality of logical addresses to corresponding physical address locations in the DRAM. Each translated physical address is comprised of a row address and a column address. A physical address, including the row and column addresses, is accessed from the LSR. To access the DRAM paragraph at the accessed physical address, the row in the DRAM at the accessed row address location is strobed to setup and precharge the row. Following, all columns in the DRAM paragraph at the accessed physical address are strobed. After strobing the columns in a DRAM paragraph, the next physical address in the LSR, including the next row and column addresses, is accessed.

Abstract: The present disclosure concerns a method and apparatus for mapping each of a plurality of logical addresses to a physical address identifying a location in a memory device. The memory device has a plurality of columns and rows, wherein each row has a plurality of data paragraphs including data and at least one parity paragraph including parity data. Each paragraph is comprised of a plurality of contiguous columns. A physical address identifies a location of a paragraph in the memory device. To map the logical addresses to physical addresses, a determination must be made as to whether the row and column portions of each logical address identify a physical address location including parity data. If a logical address identifies a physical address location in the memory device including parity data, then the logical address is incremented until the row and column portions of the logical address identify a physical address location not including parity data.