Patents by Inventor Frank Zudock
Frank Zudock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030200Abstract: In an embodiment, a semiconductor package includes a lower surface having a low voltage contact pad, a high voltage contact pad, an output contact pad, and at least one control contact pad. The semiconductor package further includes a half-bridge circuit including a first transistor device having a first major surface and a second transistor device having a first major surface, the first and second transistor devices being electrically coupled in series at an output node, and a control device that is electrically coupled to the first transistor device and the second transistor device. The first major surface of the first transistor device and of the second transistor device are arranged substantially perpendicularly to the lower surface of the semiconductor package.Type: ApplicationFiled: July 13, 2023Publication date: January 25, 2024Inventors: Christian Irrgang, Thomas Behrens, Ludwig Heitzer, Josef Hoglauer, Thorsten Meyer, Thorsten Scharf, Frank Zudock
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Publication number: 20230117806Abstract: Semiconductor packages and methods for manufacturing are disclosed. In one example, a method for manufacturing a semiconductor package includes providing an electrically conductive chip carrier including a mounting surface and a protrusion extending out of the mounting surface. At least one semiconductor chip is arranged on the mounting surface. The method further includes encapsulating the protrusion and the at least one semiconductor chip in an encapsulation material, wherein surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface remain uncovered by the encapsulation material. An electrical redistribution layer is formed over the surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface. The electrical redistribution layer provides an electrical connection between the protrusion and the at least one semiconductor chip.Type: ApplicationFiled: September 26, 2022Publication date: April 20, 2023Applicant: Infineon Technologies AGInventors: Thorsten MEYER, Thomas BEHRENS, Christian IRRGANG, Frank ZUDOCK
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Patent number: 10157869Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.Type: GrantFiled: October 14, 2016Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
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Publication number: 20170103956Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.Type: ApplicationFiled: October 14, 2016Publication date: April 13, 2017Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
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Patent number: 9472515Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.Type: GrantFiled: March 11, 2014Date of Patent: October 18, 2016Assignee: INTEL CORPORATIONInventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
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Publication number: 20150262866Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 11, 2014Publication date: September 17, 2015Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
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Publication number: 20150187608Abstract: A die package architecture with an embedded die and simplified redistribution layer is described. In one example a method includes attaching a front side of a die to a temporary carrier panel applying a molding compound around the die and over the temporary carrier panel. Removing the temporary carrier, applying a metal routing layer over the front side of the die and the molding compound, and applying a connection array to the metal routing layer.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Inventors: Sanka GANESAN, Thorsten MEYER, Robert L. SANKMAN, Mark T. BOHR, Frank ZUDOCK
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Patent number: 8786105Abstract: A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.Type: GrantFiled: January 11, 2013Date of Patent: July 22, 2014Assignee: Intel Mobile Communications GmbHInventors: Thorsten Meyer, Sven Albers, Christian Geissler, Andreas Wolter, Markus Brunnbauer, David O'Sullivan, Frank Zudock, Jan Proschwitz
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Publication number: 20140197530Abstract: A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.Type: ApplicationFiled: January 11, 2013Publication date: July 17, 2014Applicant: Intel Mobile Communications GmbHInventors: Thorsten Meyer, Sven Albers, Christian Geissler, Andreas Wolter, Markus Brunnbauer, David O'Sullivan, Frank Zudock, Jan Proschwitz
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Patent number: 8093711Abstract: A semiconductor device includes a semiconductor chip having a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face, encapsulation material at least partially encapsulating the semiconductor chip, and a first metal layer disposed over the encapsulation material and connected with the through-connection.Type: GrantFiled: February 2, 2009Date of Patent: January 10, 2012Assignee: Infineon Technologies AGInventors: Frank Zudock, Thorsten Meyer, Markus Brunnbauer, Andreas Wolter
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Publication number: 20100193928Abstract: A semiconductor device includes a semiconductor chip having a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face, encapsulation material at least partially encapsulating the semiconductor chip, and a first metal layer disposed over the encapsulation material and connected with the through-connection.Type: ApplicationFiled: February 2, 2009Publication date: August 5, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Frank Zudock, Thorsten Meyer, Markus Brunnbauer, Andreas Wolter