Abstract: A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line.

Abstract: The disclosed embodiments provide a system that tracks and compensates for input signal noise at a receiver of a data communication channel. In particular embodiments, the receiver of the data communication link receives an input signal which comprises two signal levels. Next, for each of the two signal levels, the system generates an error signal by comparing the input signal value of the signal level with an expected signal value for the signal level. The system then updates a threshold signal value based on at least one of the two error signals associated with the two signal levels. Finally, the system compensates for input signal noise in the received input signal using the updated threshold signal value.

Abstract: In the optical device, a ring-resonator modulator, having an adjustable resonance (center) wavelength, optically couples an optical signal that includes the carrier wavelength from an input optical waveguide to an output optical waveguide. A monitoring mechanism in the optical device, which is optically coupled to the output optical waveguide, monitors a performance metric of an output optical signal from the output waveguide. For example, the monitoring mechanism may monitor: an average optical power associated with the output optical signal, and/or an amplitude of the output optical signal. Moreover, control logic in the optical device adjusts the resonance wavelength based on the monitored performance metric so that the performance metric is optimized.

Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.

Abstract: A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line.

Abstract: The disclosed embodiments provide a system that tracks and compensates for input signal noise at a receiver of a data communication channel. In particular embodiments, the receiver of the data communication link receives an input signal which comprises two signal levels. Next, for each of the two signal levels, the system generates an error signal by comparing the input signal value of the signal level with an expected signal value for the signal level. The system then updates a threshold signal value based on at least one of the two error signals associated with the two signal levels. Finally, the system compensates for input signal noise in the received input signal using the updated threshold signal value.

Abstract: An optical device that includes a wavelength-sensitive optical component, which has an associated thermal time constant, is described. Note that an operating wavelength of the wavelength-sensitive optical component is a function of several physical parameters including temperature. Moreover, the optical device includes a heating mechanism that provides heat to the wavelength-sensitive optical component. Furthermore, the optical device includes a driver circuit that provides a pulse-width modulated signal to the heating mechanism. Note that an average pulse-width modulated heat provided by the heating mechanism, and which corresponds to the pulse-width modulated signal, thermally tunes the wavelength-sensitive optical component to a target operating wavelength. Additionally, note that the target operating wavelength corresponds to a target operating temperature of the wavelength-sensitive optical component.

Abstract: An optical receiver is described. This optical receiver has two operating modes: a calibration mode and a normal mode. During the normal mode, switches are used to electrically couple an input of a transimpedance amplifier (TIA) to an optical-to-electrical (OE) converter that receives an optical signal and provides a corresponding analog electrical signal. Moreover, during the calibration mode, the switches are used to electrically isolate the input of the TIA from the OE converter while maintaining a feedback path from an output of the TIA to the input of the TIA, thereby ensuring proper bias of the TIA during calibration. Furthermore, a frequency response of the TIA during the normal mode is substantially unchanged over an operating bandwidth of the TIA by the capability to electrically isolate the input of the TIA from the OE converter during the calibration mode.

Abstract: An optical device that includes a wavelength-sensitive optical component, which has an associated thermal time constant, is described. Note that an operating wavelength of the wavelength-sensitive optical component is a function of several physical parameters including temperature. Moreover, the optical device includes a heating mechanism that provides heat to the wavelength-sensitive optical component. Furthermore, the optical device includes a driver circuit that provides a pulse-width modulated signal to the heating mechanism. Note that an average pulse-width modulated heat provided by the heating mechanism, and which corresponds to the pulse-width modulated signal, thermally tunes the wavelength-sensitive optical component to a target operating wavelength. Additionally, note that the target operating wavelength corresponds to a target operating temperature of the wavelength-sensitive optical component.

Abstract: An optical receiver is described. This optical receiver has two operating modes: a calibration mode and a normal mode. During the normal mode, switches are used to electrically couple an input of a transimpedance amplifier (TIA) to an optical-to-electrical (OE) converter that receives an optical signal and provides a corresponding analog electrical signal. Moreover, during the calibration mode, the switches are used to electrically isolate the input of the TIA from the OE converter while maintaining a feedback path from an output of the TIA to the input of the TIA, thereby ensuring proper bias of the TIA during calibration. Furthermore, a frequency response of the TIA during the normal mode is substantially unchanged over an operating bandwidth of the TIA by the capability to electrically isolate the input of the TIA from the OE converter during the calibration mode.

Abstract: An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit.

Abstract: A technique for calibrating an optical receiver is described. During this technique, a front-end circuit in the optical receiver receives an optical signal that corresponds to a sequence with alternating groups of symbol types that correspond to binary values, where durations of the groups of a given symbol type, which can correspond to a first binary value or a second binary value, progressively decrease during the sequence. Then, the output of the feedback circuit is adjusted based at least on the sequence. When the durations of groups corresponding to the first binary value and the second binary value reach their minimum values in the sequence, a calibration value corresponding to the output of the feedback circuit is stored for use during a normal operating mode of the optical receiver.

Abstract: A technique for calibrating an optical receiver is described. During this technique, a front-end circuit in the optical receiver receives an optical signal that corresponds to a sequence with alternating groups of symbol types that correspond to binary values, where durations of the groups of a given symbol type, which can correspond to a first binary value or a second binary value, progressively decrease during the sequence. Then, the output of the feedback circuit is adjusted based at least on the sequence. When the durations of groups corresponding to the first binary value and the second binary value reach their minimum values in the sequence, a calibration value corresponding to the output of the feedback circuit is stored for use during a normal operating mode of the optical receiver.

Abstract: An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit.

Abstract: Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more of the asynchronous signals. This triggering module has a continuous mode of operation and a single-shot mode of operation. A timing module within the debug circuit has a timing range exceeding a pre-determined value, and is configured to provide signals corresponding to a first time base or signals corresponding to a second time base. Furthermore, control logic within the debug circuit is configured to select a mode of operation and a given time base for the debug circuit, which is either the first time base or the second time base.

Abstract: A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing.

Abstract: Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more of the asynchronous signals. This triggering module has a continuous mode of operation and a single-shot mode of operation. A timing module within the debug circuit has a timing range exceeding a pre-determined value, and is configured to provide signals corresponding to a first time base or signals corresponding to a second time base. Furthermore, control logic within the debug circuit is configured to select a mode of operation and a given time base for the debug circuit, which is either the first time base or the second time base.

Abstract: A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing.