Patents by Inventor Franklin Baez

Franklin Baez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10706204
    Abstract: A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Audet, Alain Ayotte, Franklin Baez, Anson Call, Deana Cosmadelis, Jason Lee Frankel, Kevin Grosselfinger, Roxan Lemire, Marek Andrzej Orlowski, Gilles Poitras, Paul Robert Walling
  • Publication number: 20200104454
    Abstract: A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 2, 2020
    Inventors: Jean Audet, Alain Ayotte, Franklin Baez, Anson Call, Deana Cosmadelis, Jason Lee Frankel, Kevin Grosselfinger, Roxan Lemire, Marek Andrzej Orlowski, Gilles Poitras, Paul Robert Walling
  • Publication number: 20060044030
    Abstract: The present invention provides for compensation of leakage charge in a PLL. A first plurality and second plurality of charge pumps has a source charge pump and a sink charge pump, and each charge pump has its own switch. A first node is coupled between at least one source charge pump and at least one sink charge pump. A second node coupled between at least one source charge pump and at least one sink charge pump. A PLL filter is coupled to the first node. A dummy filter is coupled to the second node. A first input of a differential mode sensor is coupled to the PLL filter. A second input of a differential mode sensor is coupled to the dummy filter. A first input of a common mode sensor is coupled to the dummy filter. A second input of a common mode sensor coupled to the PLL filter.
    Type: Application
    Filed: August 26, 2004
    Publication date: March 2, 2006
    Applicants: International Business Machines Corporation, Toshiba America Electronic Components, Inc., Kabushiki Kaisha Toshiba
    Inventors: Franklin Baez, David Boerstler, Eskinder Hailu, Kazuhiko Miki
  • Publication number: 20050156640
    Abstract: An apparatus, a method, and a computer program are provided for correcting charge in a Phased Lock Loop (PLL). Typically, PLL's utilize a Low Pass Filter (LPF). However, as a result of improvement of Complimentary Metal-Oxide on a Semiconductor (CMOS) technology charge leakage has become prevalent within LPFs. As a result, the method, apparatus, and computer program provide a device and/or methodology for correcting for charge leakage.
    Type: Application
    Filed: January 16, 2004
    Publication date: July 21, 2005
    Applicant: International Business Machines Corporation
    Inventors: David Boerstler, Franklin Baez, Eskinder Hailu
  • Patent number: 6327552
    Abstract: A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters. Specifically, an embodiment of the present invention provides a method and/or computer program product for determining optimal values for the design parameters of a circuit block, which result in optimally assigned delay targets for datapath blocks at the minimum power/area point. The problem/solution space is extended to solve the problem of figuring out the best possible implementation, for example, static vs dynamic, for each datapath block. Based on parameter functions, which relate to the design parameters for circuits in the circuit block, the design parameters are optimized to satisfy the design constraints.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: December 4, 2001
    Assignee: Intel Corporation
    Inventors: Mahadevamurty Nemani, Franklin Baez
  • Publication number: 20010032067
    Abstract: A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters.
    Type: Application
    Filed: December 28, 1999
    Publication date: October 18, 2001
    Inventors: MAHADEVAMURTY NEMANI, FRANKLIN BAEZ