Abstract: An integrated circuit is made with transistors having varying characteristics in the same well. One transistor, which is particularly useful as an I/O device, has a relatively deep source/drain with a relatively thick gate dielectric. The well doping is selected so that this transistor has low leakage. Another transistor type, which is particularly useful for low voltage analog purposes, has a relatively thin gate dielectric and the relatively deep source/drain. A third transistor type, which is particularly suited for high density and low power operation, has a relatively shallow source/drain, the relatively thin gate dielectric, and a high dose halo implant. A fourth transistor type, which may also be present for high-speed operations, has the relatively thin gate dielectric, the relatively shallow source/drain, and may have a halo implant. The halo implant will be of a lower dosage than the halo implant for the third transistor type.

Abstract: The semiconductor device has a trench isolation between a P-well and N-well. This trench isolation region is formed of oxide which during the course of the formation of the P and N well is doped with P-type and N-type dopants. Thus the trench has a P-type doped region and an N-type doped region which are typically phosphorous and boron. After the P and N well are formed, a rapid thermal anneal is applied to the device structure. This has the effect of causing the phosphorous doped and boron doped portions of the trench oxide to be etched at substantially the same rate. After this RTA step, gate oxide is formed over the P and N well. The following formation of polysilicon gates results in a relatively flat gate over transistor structure. This avoids corner leakage which is a problem with trench isolation.

Abstract: An integrated circuit is made with transistors having varying characteristics in the same well. One transistor, which is particularly useful as an I/O device, has a relatively deep source/drain with a relatively thick gate dielectric. The well doping is selected so that this transistor has low leakage. Another transistor type, which is particularly useful for low voltage analog purposes, has a relatively thin gate dielectric and the relatively deep source/drain. A third transistor type, which is particularly suited for high density and low power operation, has a relatively shallow source/drain, the relatively thin gate dielectric, and a high dose halo implant. A fourth transistor type, which may also be present for high-speed operations, has the relatively thin gate dielectric, the relatively shallow source/drain, and may have a halo implant. The halo implant will be of a lower dosage than the halo implant for the third transistor type.

Abstract: The semiconductor device has a trench isolation between a P-well and N-well. This trench isolation region is formed of oxide which during the course of the formation of the P and N well is doped with P-type and N-type dopants. Thus the trench has a P-type doped region and an N-type doped region which are typically phosphorous and boron. After the P and N well are formed, a rapid thermal anneal is applied to the device structure. This has the effect of causing the phosphorous doped and boron doped portions of the trench oxide to be etched at substantially the same rate. After this RTA step, gate oxide is formed over the P and N well. The following formation of polysilicon gates results in a relatively flat gate over transistor structure. This avoids corner leakage which is a problem with trench isolation.

Abstract: A method of chemical-mechanical polishing of a semiconductor device utilizes a combination of polishing steps, including a first step using a first slurry containing an abrasive component (i.e., mechanical component) and a chemical component (i.e., chemical reactants), and a second polishing step using a second slurry having a reduced amount of the abrasive component. The method is carried out with respect to metal (39), such as copper, deposited on a dielectric layer (34) and the first polishing step is stopped before the entirety of the metal overlying the dielectric layer is removed. In one embodiment, the second slurry has no abrasive component.

Abstract: A method for forming an integrated circuit with a planarized dielectric is disclosed. Runners and gates are covered with a protective dielectric layer. Then a conventional dielectric is deposited and planarized over the entire circuit surface. When windows are opened to runners and to source/drain regions, the protective dielectric helps to slow the etch process over the runner, thus protecting the runner from damage during the extra time required for the etch process to reach the source or drain.