Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

Abstract: An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.

Abstract: An integrated circuit (IC) chip carrier includes one or more internal metal planes. A dedicated metal plane (DMP) may be formed upon a metal plane dielectric layer. The metal plane dielectric layer may be formed upon a first dielectric layer that is formed upon an IC chip carrier core. The DMP may be formed of the same or different material relative to the material of the wires of the IC chip carrier. The side surfaces of the DMP may be coplanar with associated side surfaces of the IC chip carrier. The DMP may transfer heat from the IC chip horizontally to its side surfaces. A decoupling capacitor is externally connected to the IC chip carrier and is electrically connected to the DMP. By connecting the decoupling capacitor to the DMP, the decoupling capacitor may further reduce inductance and noise within the IC chip system.

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

Abstract: In one embodiment of the invention, parameter functions for a plurality of circuits in a subsystem are created. The subsystem has design constraints. Each one of the parameter functions corresponds to each one of the circuits. The parameter functions represent a relationship among design parameters of the subsystem. The design parameters include constraint and optimizing sets. Initial design points are selected on the parameter functions having a first sum of the constraint set and a second sum of the optimizing set such that the first sum satisfies the design constraints. New design points are selected on the parameter functions such that the second sum is improved within the design constraints.

Abstract: The present invention is a method and machine readable medium for determining optimal values of design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. Parameter functions are created for the corresponding circuits. The parameter functions represent a relationship among the design parameters. The design parameters are optimized based on the parameter functions to satisfy the design constraints.