Abstract: The present invention provides for compensation of leakage charge in a PLL. A first plurality and second plurality of charge pumps has a source charge pump and a sink charge pump, and each charge pump has its own switch. A first node is coupled between at least one source charge pump and at least one sink charge pump. A second node coupled between at least one source charge pump and at least one sink charge pump. A PLL filter is coupled to the first node. A dummy filter is coupled to the second node. A first input of a differential mode sensor is coupled to the PLL filter. A second input of a differential mode sensor is coupled to the dummy filter. A first input of a common mode sensor is coupled to the dummy filter. A second input of a common mode sensor coupled to the PLL filter.

Abstract: An apparatus, a method, and a computer program are provided for correcting charge in a Phased Lock Loop (PLL). Typically, PLL's utilize a Low Pass Filter (LPF). However, as a result of improvement of Complimentary Metal-Oxide on a Semiconductor (CMOS) technology charge leakage has become prevalent within LPFs. As a result, the method, apparatus, and computer program provide a device and/or methodology for correcting for charge leakage.