Abstract: A memory system in accordance with the invention includes a programmable non-volatile memory that contains a security indication and program instructions. A volatile register is also provided. Memory interface logic circuitry operates responsive to the contents of the volatile register, to selectively allow access to the memory. Security indication copying circuitry receives a reset signal for the memory system. In response to the reset signal, the copying circuitry causes the security indication to be copied into the volatile register as the contents thereof.

Abstract: Described is a level-detection circuit having hysteresis and which may be powered down without losing the last state of the circuit. The level-detection circuit includes a first detection circuit, a trip-level adjustment circuit, and a second detection circuit. The first detection circuit may be essentially an inverter, with the output signal of the inverter fed to an input of the second detection circuit. The trip-level adjustment circuit is connected to the output signal and has control connections tied to the input signal. The trip-level adjustment circuit also includes control connections tied to the output signal of the circuit. In short, the trip-level adjustment circuit is configured such that one element of the trip-level adjustment circuit is connected in parallel with one element of the inverter of the first detection circuit when the input signal moves from a one potential to another potential.

Abstract: Automatic synchronization occurs between a master interrupt controller and a slave interrupt controller. A first state machine counts the number of continuous low bits on a serial data line, and reports this count to a second state machine. The second state machine, employs an intermediate TRANSITION state. While the slave is in the IDLE state (as indicated by the second STATE machine), a low on the serial data line for one cycle causes the second state machine to go into the TRANSITION state. In the TRANSITION state, the second state machine employs the count value generated by the first state machine. If the count value indicates less than four cycles, then there is considered to have been a STOP frame or serial IRQ data, and the second state machine goes back into the IDLE state. Alternately, if the count value indicates four or more cycles, then there is considered to have been a START frame and the second state machine goes into the shift IRQ state.

Abstract: A system and method for selecting a post-reset operating mode for a microcontroller. The system of this invention includes a mode indicating means to communicate to the microcontroller the desired post-reset operating mode. These means may include pin(s), and/or bit flags in main memory or register. A mode selection logic circuit receives the mode detector information. If the program code corresponding to the desired operating mode has a starting address in main memory different from the default starting address of the first fetch instruction to the CPU, then the mode selection logic disables the program memory to prevent the first instruction fetch by the CPU, and instead, inserts a surrogate branch instruction onto the data bus causing the CPU to BRANCH to the starting address of the program code corresponding to the desired post-reset operating mode.