Abstract: A radiation hardened drain-source protected MNOS transistor is disclosed. A layer of silicon oxide overlies the channel and the junctions formed by the intersections of the drain and source regions with the channel. Drain and source protection is provided by relatively thick portions of the silicon oxide layer which overlie the junctions formed by the drain and source regions and the channel. The portion of the silicon oxide layer overlying the central section of the channel is thinner than the remainder of this layer.A silicon nitride layer and an electrically conductive layer forming the gate electrode overlie the thinner portion of the silicon oxide layer to complete the MNOS transistor. The conductive layer forming gate electrode of the transistor is in electrical contact with both the silicon nitride and the silicon oxide layers.

Abstract: A processing technique utilizing two separate silicon nitride depositions (one to form the memory regions and the second to form the nonmemory regions) is employed to provide a radiation hard drain source protected memory transistor. The amount of silicon dioxide used in the nonmemory regions is also minimized. A typical device comprises a mesa etched from a silicon-on-sapphire (SOS) wafer into which P+ source and drain regions are implanted. A 100 A layer of silicon dioxide and a second 1000 A layer of nonmemory silicon nitride covers the mesa and the two layers are etched to define a substrate gate window. The gate window is covered by a 25 A layer of tunneling oxide A final 500 A layer of memory silicon nitride covers the mesa structure. Contact windows are etched to accommodate source, drain and gate interconnect electrodes.

Abstract: An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions.

Abstract: A coherent sampled CMOS readout circuit and signal processor coupled to a CCD shift register operated by a two-phase minority carrier transfer clock system. The invention comprises a multiplex MIS switch, a reverse biased collection diode, an N channel MOSFET reset switch, a P channel MOSFET electrometer amplifier, and a sample and hold circuit, the configuration having four distinct operational timing subintervals within a clock period wherein the charge is shifted from one shift register bit to another and finally to the output bit. This removes the Nyquist noise associated with the reset switch, suppresses switching transients and 1/f surface noise to thereby improve the signal to noise ratio, i.e., dynamic range, for a CCD array and readout system.