Abstract: The invention relates to a method and apparatus in duplex transmission of digital information between subscribers connected to terminals associated with each other in a telecommunication network of the time multiplex type in which information is transmitted in the form of binary words in specially assigned time slots, of carrying out with the aid of parity check, during traffic in progress, through-connection testing for checking that a correct connection has been set up after a switching path has been established. The through-connection check is started and detected in the same station (terminal). After detected correct parity, which is done with the aid of a parity check means (M1) and a comparison circuit (OR), there is generated a parity bit with intentional incorrect polarity for sending on the line towards the next station. Generation of desired parity is done with the aid of an apparatus including a local processor (MP), a control memory (CM), a counter (TR) and said comparison circuit.

Abstract: The disclosure describes a control memory for addressing inlet and outlet switching stages of a three stage digital switch. The control memory comprises two identical random access memories (RAM's) each having an address storage capacity equal to half the number of simplex connections which can be made through either stage of the switch. The arrangement described allows a large saving in the number of memory bits necessary to address the inlet and outlet switching stages and enables fast access of the control memory for the purpose of establishing or terminating connections.