Abstract: A hybrid matching approach can be used for computer vision that balances accuracy with speed and resource consumption. Stereoscopic image data can be rectified and downsampled, then analyzed using a semi-global matching (SGM) process. The use of downsampled images greatly reduces time and bandwidth requirements, while providing high accuracy disparity results. These disparity results can be provided as external hints to a fast module that can perform a robust matching process in the time needed for applications such as real time navigation. The external hints can be used, along with potentially other hints, to define a search space for use by the fast module, which can result in higher quality disparity results obtained within specified timing constraints and with limited resources. The disparity results can be used to determine distances to various objects, as may be important for vehicle navigation or robotic task performance.

Abstract: The present invention provides an apparatus for interpolation which is able to process input data with multiple video standards without sacrificing chip area. The interpolation unit comprises: a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation unit. The present invention also provides a motion compensation unit and a decoder for processing multiple video standards.

Abstract: The present invention provides an apparatus for interpolation which is able to process input data with multiple video standards without sacrificing chip area. The interpolation unit comprises: a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation unit. The present invention also provides a motion compensation unit and a decoder for processing multiple video standards.

Abstract: A system and method to provide a processor with a dynamic instruction set and decoder is provided. One embodiment provides a micro-processor with a dynamic instruction set, the instruction set is updated on the fly. A single instruction can be interpreted in many different ways depending on the current configuration of the instruction decoder. This configuration is not restricted to a single or a few modes, but can take many different values. The configuration can be adapted by explicit instructions in the instruction stream or as a side effect of other instructions being executed. The advantage of updating the instruction set is in the coding efficiency. E.g., the total number of instructions that can be executed by the functional units may exceed the instruction set size, which can be limited by the maximum instruction (bit string) length.

Abstract: Techniques are described for dynamically controlling the execution of operations within a multi-operation instruction, such as a very long instruction word (VLIW). A programmable processor fetches and executes a first instruction having an operation mask. Based on the operation mask, the processor selectively executes one or more operations within a second instruction. Individual operations within a multi-operation instruction can be selectively enabled and disabled, which is advantageous in many situations, including event handling and code debugging.