Abstract: A data processor that can perform instructions in parallel on respective fields in an operand includes a respective multiplexer for each of the respective fields. Each respective multiplexer is controlled by condition data for a particular field, preferably from an addressable storage unit. The condition may take three or more values for each field, which allows multiplexing between three or more values, reflecting a less than, equal to, or greater than relation between respective compare inputs. The inputs of the multiplexers can share read ports to a register file with more than one functional unit connected to only two read ports.

Abstract: A data processor uses storage units that are subdivisible into predetermined fields for executing instructions that cause the data processor to handle numbers from respective ones of the fields separately. The processor has an instruction that addresses a first and a second one of the storage units. In response the data processor takes a first and second group of successive bits from a first and second one of the fields of the first one of the storage units, places the first and second groups of successive bits at respective shifted positions both in the same field in a result storage unit, a bit position distance between the shifted positions being controlled by a content of the second one of the storage units.

Abstract: A data processing device provides for registers which can be formatted as segments containing numbers to which operations can be applied in SIMD fashion. In addition it is possible to perform operations which combine different segments of one register or segments at different positions in the different registers. By providing specially selected it is thus made possible to perform multidimensional separable transformations (like the 2-dimensional IDCT) without transposing the numbers in the registers.

Abstract: A method and a device for determining the permissibility of a series of a1. . . an end symbols as being derivable by means of a set of production rules on the basis of a context-free grammar G are described. The derivation takes place by assigning dotted rules to elements Ti,j (0.ltoreq.i.ltoreq.j.ltoreq.n) (FIG. 1) of a recognition matrix by means of scan, complete and predict operations. The number of operations is of the order of (n.sup.3). In a first embodiment (n+1) processing modules (FIG. 8) are set up and the successive operations can be limited to a number of the order of (n.sup.2) . In a second embodiment 1/2(n+1)(n+2)-1 processing modules are set up and the successive operations can be limited to a number of the order of (n). The method may be applied in a translation machine.