Patents by Inventor Franz Gisin

Franz Gisin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10757800
    Abstract: A circuit board transmission line structures has microstrip or stripline transmission line geometries and cross-hatch patterned return planes. The cross-hatch design structure of the return planes and the relative position of the cross-hatch pattern to the transmission lines are configured to increase the usable bandwidth of the transmission lines. By properly adjusting the size and shape of the cross-hatch pattern, the performance of the microstrip and stripline transmission lines can be largely restored to the performance where continuous, solid return planes are used.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: August 25, 2020
    Assignee: Flex Ltd.
    Inventors: Mark Bergman, Franz Gisin
  • Patent number: 10712398
    Abstract: A measuring system and method is configured to analyze numerous different types of interconnects having varying degrees of complexity. The measuring system and method characterizes an interconnect to be tested by a predefined reflection coefficient signature. Each specific interconnect is predefined by a reflection coefficient signature that is unique to that specific interconnect. Once the reflection coefficient signature is defined, a corresponding reflection envelope is defined which defines boundary limits about the reflection coefficient signature. Subsequent testing of the specific interconnect results in a measured reflection coefficient curve, which is compared to the corresponding reflection envelope. The specific interconnect under test is considered acceptable if the values of the measured reflection coefficient curve do not fall outside the reflection envelope.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 14, 2020
    Assignee: Multek Technologies Limited
    Inventor: Franz Gisin
  • Patent number: 8222537
    Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: July 17, 2012
    Assignee: Sanmina-Sci Corporation
    Inventors: George Dudnikov, Jr., Franz Gisin
  • Patent number: 8156640
    Abstract: The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.
    Type: Grant
    Filed: October 4, 2008
    Date of Patent: April 17, 2012
    Assignee: Sanmina-SCI Corporation
    Inventors: George Dudnikov, Jr., Franz Gisin, Gregory J. Schroeder
  • Patent number: 7688598
    Abstract: The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: March 30, 2010
    Assignee: Sanmina-SCI Corporation
    Inventors: George Dudnikov, Jr., Franz Gisin, Gregory J. Schroeder
  • Publication number: 20090288874
    Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.
    Type: Application
    Filed: June 11, 2009
    Publication date: November 26, 2009
    Applicant: SANMINA SCI CORPORATION
    Inventors: George Dudnikov, JR., Franz Gisin
  • Patent number: 7593203
    Abstract: Protection for sensitive components on a printed circuit board by selectively depositing transient protection material on one or more layers of the printed circuit board is disclosed.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: September 22, 2009
    Assignee: Sanmina-SCI Corporation
    Inventors: George Dudnikov, Jr., Franz Gisin, Gregory J. Schroeder
  • Publication number: 20090025213
    Abstract: The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.
    Type: Application
    Filed: October 4, 2008
    Publication date: January 29, 2009
    Applicant: SANMINA SCI CORPORATION
    Inventors: George Dudnikov, JR., Franz Gisin, Gregory J. Schroeder
  • Patent number: 7457132
    Abstract: Vias are used in multilayer printed circuit boards to route electrical interconnects between layers. Some via constructions embodiments result in the formation of a via-stub section. Via stub sections can distort signals passing through the interconnect and decrease the usable bandwidth of the interconnect. To minimize distortion and increase bandwidth, one or more terminating elements can be attached to the unterminated end of the via-stub section. The impedance terminating element may include, by way of non-limiting example, one or more resistors, capacitors, and/or inductors between the via stub and a ground layer. The impedance terminating element may be formed internally to the PCB or mounted to the PCB surface.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: November 25, 2008
    Assignee: Sanmina-SCI Corporation
    Inventors: Franz Gisin, Christopher Herrick
  • Publication number: 20070294890
    Abstract: A printed circuit board with improved signal integrity for one or more differential signal pairs incorporates one or more conductive regions. In an exemplary embodiment, via structures for the differential pair that interconnect signal traces are isolated from the conductive region by an antipad area around the via structures and a conductive bridge. In alternate embodiment, an antipad area around the via structures includes a bridge between the via structures. The antipad area may comprise, by way of non-limiting example, a clipped circular aperture or a modified rectangular aperture. The bridge may, by non-limiting examples, comprise a portion of the conductive region to permit impedance tailoring of the differential pair with respect to the conductive region.
    Type: Application
    Filed: June 28, 2007
    Publication date: December 27, 2007
    Applicant: Sanmina-SCI Corporation
    Inventors: Franz Gisin, Greg Schroeder
  • Patent number: 7249337
    Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. According to one embodiment of the present invention, the method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. In certain embodiments, the process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: July 24, 2007
    Assignee: Sanmina-SCI Corporation
    Inventors: Franz Gisin, William Panos, Mahamud Khandokar
  • Publication number: 20070091581
    Abstract: Vias are used in multilayer printed circuit boards to route electrical interconnects between layers. Some via constructions embodiments result in the formation of a via-stub section. Via stub sections can distort signals passing through the interconnect and decrease the usable bandwidth of the interconnect. To minimize distortion and increase bandwidth, one or more terminating elements can be attached to the unterminated end of the via-stub section. The impedance terminating element may include, by way of non-limiting example, one or more resistors, capacitors, and/or inductors between the via stub and a ground layer. The impedance terminating element may be formed internally to the PCB or mounted to the PCB surface.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventors: Franz Gisin, Christopher Herrick
  • Publication number: 20060199390
    Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.
    Type: Application
    Filed: March 6, 2006
    Publication date: September 7, 2006
    Inventors: George Dudnikov, Franz Gisin
  • Publication number: 20060181827
    Abstract: Protection for sensitive components on a printed circuit board by selectively depositing transient protection material on one or more layers of the printed circuit board is disclosed.
    Type: Application
    Filed: February 16, 2006
    Publication date: August 17, 2006
    Inventors: George Dudnikov, Franz Gisin, Gregory Schroeder
  • Publication number: 20060181826
    Abstract: The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.
    Type: Application
    Filed: February 16, 2006
    Publication date: August 17, 2006
    Inventors: George Dudnikov, Franz Gisin, Gregory Schroeder
  • Publication number: 20060151869
    Abstract: A printed circuit board with improved signal integrity for one or more differential signal pairs incorporates one or more conductive regions. In an exemplary embodiment, via structures for the differential pair that interconnect signal traces are isolated from the conductive region by an antipad area around the via structures and a conductive bridge. In alternate embodiment, an antipad area around the via structures includes a bridge between the via structures. The antipad area may comprise, by way of non-limiting example, a clipped circular aperture or a modified rectangular aperture. The bridge may, by non-limiting examples, comprise a portion of the conductive region to permit impedance tailoring of the differential pair with respect to the conductive region.
    Type: Application
    Filed: November 17, 2005
    Publication date: July 13, 2006
    Inventors: Franz Gisin, Greg Schroeder
  • Publication number: 20040176938
    Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. The method may involve the use of the S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis may be performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the subcircuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 9, 2004
    Applicant: Sanmina-SCI Corporation
    Inventors: Franz Gisin, William Panos, Mahamud Khandokar
  • Patent number: 5770898
    Abstract: A power management system for providing power to a main system, such as a telecommunications device, includes a number of modules that are joined by module-to-module interfaces that achieve a common EMC containment barrier. In one embodiment, a battery module defines a first EMC compartment that houses one or more backup batteries, a battery management module defines a second EMC compartment that includes circuitry such as recharging circuitry, and a power entry module includes a third EMC compartment. The power entry module has an input/output connection to the battery management module and has an AC input. An output cable extends from the power entry module to the main system. Compliant metallic module-to-module gaskets preserve EMC integrity at cable pass-throughs from the battery management module to the battery and power entry modules. The modules are mounted to a system housing in a manner that secures the modules in a desired relationship.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: June 23, 1998
    Assignee: Siemens Business Communication Systems, Inc.
    Inventors: Matthew T. Hannigan, Ronald R. Carleton, Paul Bonomo, John W. Kerr, Jr., James M. Worsham, Robin Spires, Franz Gisin, William Beyda