Abstract: A trench transistor having a semiconductor body includes a source region, a body region, a drain region electrically connected to a drain contact, and a gate trench including a gate electrode which is isolated from the semiconductor body. The gate electrode is configured to control current flow between the source region and the drain region along at least a first side wall of the gate trench. The trench transistor further includes a doped semiconductor region having dopants introduced into the semiconductor body through an unmasked part of the walls of a trench.

Abstract: A semiconductor device comprises at least one strip-shaped cell compensation region of a vertical electrical element arrangement, at least one strip-shaped edge compensation region and a bridge structure. The at least one strip-shaped cell compensation regions extends into a semiconductor substrate and comprises a first conductivity type. Further, the at least one strip-shaped cell compensation region is connected to a first electrode structure of the vertical electrical element arrangement. The at least one strip-shaped edge compensation region extends into the semiconductor substrate within an edge termination region of the semiconductor device and outside the cell region. Further, the at least one strip-shaped edge compensation region comprises the first conductivity type. The bridge structure electrically connects the at least one strip-shaped edge compensation region with the at least one strip-shaped cell compensation region within the edge termination region.

Abstract: A super-junction semiconductor device includes a junction termination area at a first surface of a semiconductor body and at least partly surrounding an active cell area. An inner part of the junction termination area is arranged between an outer part of the junction termination area and the active cell area. A charge compensation device structure includes first regions of a first conductivity type and second regions of a second conductivity type disposed alternately along a first lateral direction. First surface areas correspond to a projection of the first regions onto the first surface, and second surface areas correspond to a projection of the second regions onto the first surface. The super-junction semiconductor device further includes at least one of a first junction termination extension structure and a second junction termination extension structure.

Abstract: Disclosed is a transistor device and a method for producing thereof. The transistor device includes at least one transistor cell, wherein the at least one transistor cell includes: a source region, a body region and a drift region in a semiconductor body; a gate electrode dielectrically insulated from the body region by a gate dielectric; a field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a contact plug extending from a first surface of the semiconductor body to the field electrode and adjoining the source region and the body region.

Abstract: In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.

Abstract: The present disclosure relates to a superjunction device and a semiconductor structure having the same. The superjunction device includes a body region of a second conduction type, a drain region of a first conduction type, a drift region located between said body region and said drain region. The drift region includes first regions of a first conduction type and second regions of a second conduction type arranged alternately along a direction being perpendicular to the direction from the body region to the drain region, and a plurality of trench gate structures, each of them comprising a trench extending into said drift region from an upper surface of said body region and a gate electrode in said trench surrounded by a first dielectric layer filling said trench, and a source region of a first conduction type embedded into said body region. There is no source region along at least 10% of the total interface length between the first dielectric layer and the body region.

Abstract: A method of manufacturing a semiconductor device includes: forming field electrode structures extending in a direction vertical to a first surface in a semiconductor body; forming cell mesas from portions of the semiconductor body between the field electrode structures, including body zones forming first pn junctions with a drift zone; forming gate structures between the field electrode structures and configured to control a current flow through the body zones; and forming auxiliary diode structures with a forward voltage lower than the first pn junctions and electrically connected in parallel with the first pn junctions, wherein semiconducting portions of the auxiliary diode structures are formed in the cell mesas.

Abstract: A semiconductor device includes a first coil that is monolithically integrated in a first portion of a semiconductor body and that includes a first winding wrapping around a first core structure. A second coil is monolithically integrated in a second portion of the semiconductor body and includes a second winding wrapping around the second core structure. The first and second coils are magnetically coupled with each other. An insulator frame in the semiconductor body surrounds the first portion and excludes the second portion. High dielectric strength between the first and the second coils is achieved without patterning a backside metallization for connecting the turns of the windings and without being restricted to thin substrates.

Abstract: A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate. Additionally, the method includes connecting a carrier substrate to the oxide layer and processing a back side of the semiconductor substrate.

Abstract: A MOS transistor semiconductor component includes a semiconductor body with first and second surfaces, a first contact electrode on the first surface, a second contact electrode on the second surface, a first insulation layer separating a via region at least from a drift region, a monocrystalline semiconductor region arranged in the via region and extending between the first surface and the second surface, a gate electrode electrically connected to the first contact electrode, a source electrode electrically insulated from the gate electrode, and arranged at least partially above the first surface, and a drain electrode electrically insulated from the second contact electrode on the second surface. The MOS transistor has a gate terminal formed by the second contact electrode and electrically connected to a gate-electrode of the MOS transistor through the via region. The gate-electrode is formed next to the first surface and disposed outside the via region.

Abstract: A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.

Abstract: A super junction semiconductor device includes a semiconductor portion having strip structures in a cell area. Each strip structure has a compensation structure with first and second sections inversely provided on opposite sides of a fill structure. Each section has first and second compensation layers of complementary conductivity types. The strip structures are linear stripes extending through the cell area in a first lateral direction and into an edge area surrounding the cell area in lateral directions. Each strip structure has an end section with a termination portion in the edge area in which the first compensation layer of the first section is connected with the first compensation layer of the second section via a first conductivity layer, and the second compensation layer of the first section is connected with the second compensation layer of the second section via a second conductivity layer.

Abstract: A semiconductor device is manufactured by forming a gate electrode adjacent to a body region in a semiconductor substrate, forming a field plate trench in a main surface of the substrate, the field plate trench having an extension length in a first direction parallel to the main surface, and forming a field electrode and a field dielectric layer in the field plate trench so that the field electrode is insulated from an adjacent drift zone by the field dielectric layer. The extension length of the field plate trench in the first direction is less than double an extension length of the field electrode in a second direction that is perpendicular to the first direction and is parallel to the main surface. The extension length in the first direction is more than half the extension length in the second direction.

Abstract: A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted.

Abstract: A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.

Abstract: A trench etch mask is formed on a process surface of a semiconductor layer. By using the trench etch mask, both first trenches and second trenches are formed that extend from the process surface into the semiconductor layer. The first and second trenches alternate along at least one horizontal direction parallel to the process surface. First semiconductor regions of a first conductivity type are formed in the first trenches. Second semiconductor regions of a second, opposite conductivity type are formed in the second trenches.

Abstract: A transistor device includes: a first source region and a first drain region spaced apart from each other in a first direction of a semiconductor body; at least two gate regions arranged between the first source region and the first drain region and spaced apart from each other in a second direction of the semiconductor body; at least one drift region adjoining the first source region and electrically coupled to the first drain region; at least one compensation region adjoining the at least one drift region and the at least two gate regions; a MOSFET including a drain node connected to the first source region, a source node connected to the at least two gate region, and a gate node. Active regions of the MOSFET are integrated in the semiconductor body in a device region that is spaced apart from the at least two gate regions.

Abstract: According to various embodiments, an electronic device may include a carrier including at least a first region and a second region being laterally adjacent to each other; an electrically insulating structure arranged in the first region of the carrier, wherein the second region of the carrier is free of the electrically insulating structure; a first electronic component arranged in the first region of the carrier over the electrically insulating structure; a second electronic component arranged in the second region of the carrier; wherein the electrically insulating structure includes one or more hollow chambers, wherein the sidewalls of the one or more hollow chambers are covered with an electrically insulating material.

Abstract: A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.

Abstract: A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein.