Abstract: A pluggable, modular electronic processing component comprises a housing and programmable circuitry. The housing includes a set of conductive terminals that extend therefrom, and each terminal of the set of conductive terminals is sized and spaced to fit into a corresponding terminal socket of a distribution module. The programmable circuitry contained within the housing comprises a processor and a bus interface communicably coupled to the processor. The bus interface interfaces the pluggable, modular electronic processing component to a bus connected to via the distribution module. Further, the bus interface is coupled to a subset of the conductive terminals of the housing. Moreover, the programmable circuitry comprises a configurable input-output (or a set of configurable I/O) that is coupled to a second subset of the conductive terminals of the housing.

Abstract: A pluggable, modular electronic processing component comprises a housing and programmable circuitry. The housing includes a set of conductive terminals that extend therefrom, and each terminal of the set of conductive terminals is sized and spaced to fit into a corresponding terminal socket of a distribution module. The programmable circuitry contained within the housing comprises a processor and a bus interface communicably coupled to the processor. The bus interface interfaces the pluggable, modular electronic processing component to a bus connected to via the distribution module. Further, the bus interface is coupled to a subset of the conductive terminals of the housing. Moreover, the programmable circuitry comprises a configurable input-output (or a set of configurable I/O) that is coupled to a second subset of the conductive terminals of the housing.

Abstract: DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a planar construction and can be produced together with gate electrodes of transistors of a periphery of the cell arrangement. A depression of the substrate is provided per memory cell, a storage node of a storage capacitor being arranged in the lower region of said depression and a gate electrode of a vertical transistor being arranged in the upper region of said depression. The depressions of the memory cells are arranged between trenches filled with isolating structures. Upper source/drain regions of the transistors are arranged between two mutually adjacent isolating structures and between two mutually adjacent depressions. Lower source/drain regions are arranged in the substrate and adjoin the storage nodes. For process steps, alignment tolerances are so large that the space requirement for the memory cell can amount to 4F2.