Patents by Inventor Franz Kreupl

Franz Kreupl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9177995
    Abstract: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: November 3, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Gutsche, Franz Kreupl, Harald Seidl
  • Patent number: 9034689
    Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: May 19, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Deepak C. Sekar, Franz Kreupl, Peter Rabkin, Chu-Chen Fu
  • Patent number: 8987046
    Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Deepak C. Sekar, Franz Kreupl, Raghuveer S. Makala, Peter Rabkin
  • Patent number: 8912654
    Abstract: An integrated circuit with a substrate with a lower and an upper surface is described. A via extends between the upper and the lower surface of the substrate. The via contains a conductive filling material that comprises carbon.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: December 16, 2014
    Assignee: Qimonda AG
    Inventors: Franz Kreupl, Harry Hedler
  • Patent number: 8772749
    Abstract: In a first aspect, a metal-insulator-metal (MIM) stack is provided that includes (1) a first conductive layer comprising a silicon-germanium (SiGe) alloy; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: July 8, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Deepak Chandra Sekar, Franz Kreupl, Raghuveer S. Makala
  • Patent number: 8742387
    Abstract: An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: June 3, 2014
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Franz Kreupl, Jan Boris Philipp, Petra Majewski
  • Patent number: 8737111
    Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: May 27, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Xiying Costa, James Kai, Raghuveer S. Makala
  • Patent number: 8686419
    Abstract: A memory device in a 3-D read and write memory includes a resistance-changing layer, and a local contact resistance in series with, and local to, the resistance-changing layer. The local contact resistance is established by a junction between a semiconductor layer and a metal layer. Further, the local contact resistance has a specified level of resistance according to a doping concentration of the semiconductor and a barrier height of the junction. A method for fabricating such a memory device is also presented.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: April 1, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Deepak C Sekar
  • Patent number: 8664657
    Abstract: A circuit is disclosed. The circuit includes at least one nanostructure and a carbon interconnect formed by a substantially carbon layer, wherein the nanostructure and the carbon interconnect are directly coupled to one another.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: March 4, 2014
    Assignee: Qimonda AG
    Inventors: Georg Duesberg, Franz Kreupl, Robert Seidel, Gernot Steinlesberger
  • Patent number: 8624293
    Abstract: A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: January 7, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Abhijit Bandyopadhyay, Franz Kreupl, Andrei Mihnea, Li Xiao
  • Publication number: 20130234099
    Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.
    Type: Application
    Filed: March 21, 2013
    Publication date: September 12, 2013
    Applicant: SANDISK 3D LLC
    Inventors: Deepak C. Sekar, Franz Kreupl, Raghuveer S. Makala, Peter Rabkin, Chu-Chen Fu, Tong Zhang
  • Patent number: 8520424
    Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: August 27, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Abhijit Bandyopadhyay, Yung-Tin Chen, Chu-Chen Fu, Wipul Pemsiri Jayasekara, James Kai, Raghuveer S. Makala, Peter Rabkin, George Samachisa, Jingyan Zhang
  • Patent number: 8503229
    Abstract: Non-volatile storage elements having a P?/metal floating gate are disclosed herein. The floating gate may have a P? region near the tunnel oxide, and may have a metal region near the control gate. A P? region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P? region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: August 6, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Sanghyun Lee, Mohan Dunga, Masaaki Higashitani, Tuan Pham, Franz Kreupl
  • Patent number: 8487292
    Abstract: A non-volatile resistance-switching memory element includes a resistance-switching element formed from a metal oxide layer having a dopant which is provided at a relatively high concentration such as 10% or greater. Further, the dopant is a cation having a relatively large ionic radius such as 70 picometers or greater, such as Magnesium, Chromium, Calcium, Scandium or Yttrium. A cubic fluorite phase lattice may be formed in the metal oxide even at room temperature so that switching power may be reduced. The memory element may be pillar-shaped, extending between first and second electrodes and being in series with a steering element such as a diode. The metal oxide layer may be deposited at the same time as the dopant. Or, using atomic layer deposition, an oxide of a first metal can be deposited, followed by an oxide of a second metal, followed by annealing to cause intermixing, in repeated cycles.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: July 16, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Deepak C. Sekar, Franz Kreupl
  • Patent number: 8471360
    Abstract: In a first aspect, a method of forming a metal-insulator-metal (“MIM”) stack is provided, the method including: (1) forming a dielectric material having an opening and a first conductive carbon layer within the opening; (2) forming a spacer in the opening; (3) forming a carbon-based switching material on a sidewall of the spacer; and (4) forming a second conductive carbon layer above the carbon-based switching material. A ratio of a cross sectional area of the opening in the dielectric material to a cross sectional area of the carbon-based switching material on the sidewall of the spacer is at least 5. Numerous other aspects are provided.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: June 25, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Er-Xuan Ping, Jingyan Zhang, Huiwen Xu
  • Patent number: 8435831
    Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: May 7, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Deepak C. Sekar, Franz Kreupl, Raghuveer Makala, Peter Rabkin
  • Patent number: 8420526
    Abstract: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 16, 2013
    Assignee: Infineon Technologies AG
    Inventors: Martin Gutsche, Franz Kreupl, Harald Seidl
  • Patent number: 8395926
    Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME). The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The layers can be provided in a lateral arrangement, such as an end-to-end, face-to-face, L-shaped or U-shaped arrangement. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: March 12, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Ritu Shrivastava
  • Patent number: 8395927
    Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has a resistance-switching layer, a conductive intermediate layer, and first and second electrodes at either end of the RSME. A breakdown layer is electrically between, and in series with, the second electrode and the intermediate layer. The breakdown layer maintains a resistance of at least about 1-10 M? while in a conductive state. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: March 12, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Chu-Chen Fu, Yibo Nian
  • Patent number: 8354660
    Abstract: In a first aspect, an MIM stack is provided that includes (1) a first conductive layer comprising a first metal-silicide layer and a second metal-silicide layer; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: January 15, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Deepak Chandra Sekar, Franz Kreupl, Raghuveer S. Makala