Abstract: A method for the manufacture of integrated MOS-field effect transistor circuits in silicon gate technology and wherein diffusion source and drain zones are coated with a high melting point silicide as low-impedance printed conductors. The diffusion zones and polysilicon gates are made low-impedance through selective deposition of the metal silicide onto surfaces thereof. The selective deposition, which proceeds by use of a reaction gas eliminating hydrogen halide, simplifies the process sequence and is fully compatible with conventional silicon gate processes. Because of the high temperature stability, preferably tantalum silicide is employed. The invention is useful in the manufacture of MOS-circuits in VLSI-technology.

Abstract: The invention relates to a method for producing MOS transistors with flat source/drain zones, short channel lengths, and a self aligned contacting plane comprised of a metal silicide. In this method, the source/drain zones in the semiconductor substrate are produced by out-diffusion of the contacting plane consisting of a doped metal silicide and deposited directly on the substrate. The method serves to produce NMOS, PMOS, and in particular CMOS circuits in VLSI technology and permits a very high packing density and an independent additional wiring plane of very low resistance.