Abstract: The present disclosure provides methods and systems for reducing noise induced in one or more components in a hearing aid. The present disclosure provides methods for reducing noise induced in telecoils.

Abstract: A method and wireless communication device use a first processing unit to perform a first communication event within a first communication window by use of a first communication protocol, a second processing unit to perform a second communication event within a second communication window by use of a second communication protocol, and a wireless communication unit connected to a radio-frequency antenna to transmit and/or receive a packet wirelessly. The first and second processing units may perform the first and second communication events via the wireless communication unit. The second processing unit or the wireless communication unit may transmit an event signal to the first processing unit when performing the second communication event or receiving a packet, respectively, to allow the first processing unit to arrange the first communication window (or first communication event) with respect to the second communication window (or second communication event) to minimize interference.

Abstract: An in-the-ear hearing aid device is disclosed. The device at least one electro-acoustic transducer, and at least one sensor or at least one active electronic component. The at least one electro-acoustic transducer comprises a capsule enclosing a transducer sound active part and a transducer air volume. The transducer air volume is air volume which is enclosed by said capsule and which is in fluid-connection with said transducer sound active part. At least a portion of said at least one sensor or of said at least one active electronic component is provided within said transducer air volume.

Abstract: The present disclosure relates to detachable speaker units for hearing aid devices, and the hearing aid devices having detachable speaker units. The detachable speaker unit have at least an output transducer for providing a signal perceivable as sound to a user. The detachable speaker unit includes a memory unit storing information relating to characteristics of the output capabilities of the detachable speaker unit, such as transfer function of output transducer and/or transfer function of the entire, or parts of, assembly.

Abstract: The invention relates to a hearing device that comprises a data interface for receiving data and a memory unit for storing data. The memory unit comprises a non-static section and a static section. The static section comprises a unique key that is unique for the specific hearing device. The hearing device further comprises a verifier that is configured to process the unique key and a second key contained in first type data received via the data interface in order to determine whether the second key needs a verification criterion with respect to the unique key. The verifier is further configured to discard received first type data in the non-static section of the memory unit if the second key contained in received data does not meet the verification criterion with respect to the unique key stored in the static section of the memory unit.

Abstract: The disclosure presents a method and a wireless communication device configured to use a first communication protocol for performing a first communication event and a second communication protocol for performing a second communication event, comprising; a first processing unit may be configured to perform the first communication event within a first communication window by the use of the first communication protocol; a second processing unit may be configured to perform the second communication event within a second communication window by the use of the second communication protocol; a wireless communication unit connected to a radio-frequency antenna may be configured to transmit and/or receive a packet wirelessly, and the wireless communication unit is further connected to the second processing unit, the second processing unit may be configured to perform the second communication event of the packet via the wireless communication unit, and the wireless communication unit is further connected to the first p

Abstract: The present disclosure relates to detachable speaker units for hearing aid devices, and the hearing aid devices having detachable speaker units. The detachable speaker unit have at least an output transducer for providing a signal perceivable as sound to a user. The detachable speaker unit includes a memory unit storing information relating to characteristics of the output capabilities of the detachable speaker unit, such as transfer function of output transducer and/or transfer function of the entire, or parts of, assembly.

Abstract: The invention regards a hearing aid comprising a receiver and a signal processing device, wherein the signal processing device is electrically coupled to a connection socket operable to detachably connect the receiver to the socket and whereby the signal processing device further comprise a detector operable to detect a characteristics of the receiver which is connected to the signal processing device through the connection socket. The present invention addresses the problem of identification of individual receiver properties as well as of identifying different types of receivers.

Abstract: A method for tracing a multi-tasking embedded pipelined processor includes executing compiled code including trace controls. Tracing is initiated when the execution of the compiled code is initiated. Tracing is stopped when execution of the compiled code is completed. A trace record is formed during tracing. The trace record includes a processor mode indication, application space identity value and an instruction architecture set mode indication.

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: The invention regards a hearing aid comprising a receiver and a signal processing device, wherein the signal processing device is electrically coupled to a connection socket operable to detachably connect the receiver to the socket and whereby the signal processing device further comprise a detector operable to detect a characteristics of the receiver which is connected to the signal processing device through the connection socket. The present invention addresses the problem of identification of individual receiver properties as well as of identifying different types of receivers.

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Abstract: An interface for transferring data between a central processing unit (CPU) and a plurality of coprocessors is provided. The interface includes an instruction bus and a data bus. The instruction bus is configured to transfer instructions to the plurality of coprocessors in an instruction transfer order, where particular instructions designate and direct one of the plurality of coprocessors to transfer the data to/from the CPU. The data bus is configured to subsequently transfer the data. Data order signals within the data bus prescribe a data transfer order that differs from the instruction transfer order by prescribing a transfer corresponding to a specific outstanding particular instruction, where the data transfer order is relative to outstanding instructions. The outstanding instructions are those of the particular instructions transferred to the one of the plurality of coprocessors that have not completed a data transfer.

Abstract: A system accessible by a test access port controller via a test access port interface includes a data register. The data register is selectable based on an instruction register signal in the test access port interface. The instruction register signal is derived form an instruction register in the test access port controller. A shift register is connected to a data input and a data output in the test access port interface and to the data register. The operation of the shift register is controlled based on an indication of a state of a test access port controller state machine that is received over the test access port interface.

Abstract: A system and method for program counter and data tracing in a multi-issue processor is disclosed. Instructions are traced in program sequence order. In one embodiment instructions are traced in graduation order from a reorder buffer. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.