Abstract: A semiconductor memory configuration in a semiconductor substrate includes bit lines, word lines, and memory cells each including one memory capacitor and one MOS selection transistor having two conducting regions and a gate electrode. Each memory capacitor is connected to one of the conducting regions of the transistor. The other of the conducting regions of the transistor is connected to one of the bit lines, and the gate electrode of the transistor is connected to one of the word lines. An insulating field oxide or buried insulating oxide with substantially vertical sidewalls is provided. A trench lies adjacent to the insulating field oxide or buried insulating oxide and adjacent to one of the conducting regions. The capacitors are each disposed in one trench for each memory cell. A first insulating layer covers the inner trench wall surface. A first electrode of the capacitor is disposed perpendicular to the substrate surface on the first insulating layer completely inside the trench.

Abstract: A semiconductor memory configuration in a semiconductor substrate includes bit lines, word lines, and memory cells each including one memory capacitor and one MOS selection transistor having two conducting regions and a gate electrode. Each memory capacitor is connected to one of the conducting regions of the transistor. The other of the conducting regions of the transistor is connected to one of the bit lines, and the gate electrode of the transistor is connected to one of the word lines. An insulating field oxide or buried insulating oxide with substantially vertical sidewalls is provided. A trench lies adjacent to the insulating field oxide or buried insulating oxide and adjacent to one of the conducting regions. The capacitors are each disposed in one trench for each memory cell. A first insulating layer covers the inner trench wall surface. A first electrode of the capacitor is disposed perpendicular to the substrate surface on the first insulating layer completely inside the trench.