Abstract: A method of forming a shared global word line MRAM structure is disclosed. The method includes, etching a trench in an oxide layer formed over a substrate, depositing an first liner material, anisotropically etching the deposited first liner material leaving the first liner material on edges of the trench and physically contacting a bottom of the trench, depositing an magnetic metal liner material, anisotropically etching the deposited magnetic metal liner material leaving the magnetic metal liner material over the first liner material on edges of the trench, so that the magnetic metal liner extends to and physically contacts the bottom of the trench, depositing a conductive layer;, and chemically, mechanically polishing the conductive layer.

Abstract: The invention includes an apparatus and a method that provides a shared global word line MRAM structure. The MRAM structure includes a first bit line conductor oriented in a first direction. A first sense line conductor is oriented in a second direction. A first memory cell is physically connected between the first bit line conductor and the first sense line conductor. A global word line is oriented in substantially the second direction, and magnetically coupled to the first memory cell. A second bit line conductor is oriented in substantially the first direction. A second sense line conductor is oriented in substantially the second direction. A second memory cell is physically connected between the second bit line conductor and the second sense line conductor. The global word line is also magnetically coupled to the second memory cell. The first memory cell and the second memory cell can be MRAM devices.

Abstract: This current switch driving circuit arrangement particularly for, but not necessarily limited to, inductive device current switching, comprises a pair of output transistors constituting a driving transistor for turning ON a subsequent switching transistor and a current sinking transistor for turning OFF that switching transistor. A receiver circuit is arranged for applying one bilevel logical signal for alternatively driving the two transistors by way of intermediate circuits each having current multiplying circuitry for deriving the necessary driving currents. The intermediate circuitry is effective for toggling the current from one of the transistors to the other with provisions for insuring speedy switching action.