Patents by Inventor Fred A. Shirland

Fred A. Shirland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4191794
    Abstract: An integrated array of solar cells, each cell having a positive and a negative electrode, is disclosed. A first grid comprising a plurality of non-intersecting electrically conductive members is affixed to an insulating substrate. Each single individual member of this grid forms the negative electrode of an individual cell of the array. Overlying and affixed to the negative electrodes and the surface of the substrate between these electrodes is a semiconductor layer of a first conductivity type. Isolated (i.e., non-touching or non-abutting) semiconductor regions of a second conductivity type form a plurality of PN junctions with the semiconductor layer. These P-N junctions are the active areas of the individual cells of the array. Each of the isolated semiconductor regions of the second conductivity type is solely coupled to an individual member of another grid whose members form the positive electrodes of the individual cells.
    Type: Grant
    Filed: May 11, 1978
    Date of Patent: March 4, 1980
    Assignee: Westinghouse Electric Corp.
    Inventors: Fred A. Shirland, William J. Biter
  • Patent number: 4120705
    Abstract: A solar cell is comprised of (1) a Cu.sub.2 S thin film evaporated on a conductive substrate at an elevated temperature thereby growing a polycrystalline film of preferred orientation, and (2) an outer CdS layer grown epitaxially on the Cu.sub.2 S film.
    Type: Grant
    Filed: February 11, 1976
    Date of Patent: October 17, 1978
    Assignee: Westinghouse Electric Corp.
    Inventor: Fred A. Shirland
  • Patent number: 3975211
    Abstract: Solar cell elements are produced in accordance with the present invention in which a Cu.sub.2 S thin film is epitaxially formed on a CdS film by vacuum deposition in a heterojunction forming relationship. By a first method a Cu.sub.2 S layer on the order of 1/100 micron in thickness is formed on a CdS polycrystalline thin film by dipping in a solution of cuprous ions. The CdS film itself is less than 5 microns thick and rests on a conductive substrate. After the dipping step the Cu.sub.2 S film is increased to a thickness on the order of 1/10 micron by vapor evaporation of an additional amount of Cu.sub.2 S. By a second method both the CdS and Cu.sub.2 S are entirely vapor deposited on a substrate to achieve approximately the same final structure as the first method.
    Type: Grant
    Filed: March 28, 1975
    Date of Patent: August 17, 1976
    Assignee: Westinghouse Electric Corporation
    Inventor: Fred A. Shirland