Abstract: A data storage device includes a non-volatile semiconductor storage device and a controller that is configured to perform interleaving of small reads with large reads and small writes with large writes. In the example of reads, the controller receives a sequence of read commands including a first read command having a read size larger than a read threshold size and a second read command having a read size smaller than the read threshold size, and issue first and second read requests in succession to read data of a predetermined size less than the read threshold size, from the non-volatile semiconductor storage device. The interleaving is achieved by issuing the first read request to execute the first read command and the second read request to execute the second read command. As a result of this interleaving, the second read command will have a chance to complete earlier than the first read command even though it was received by the controller later in time.

Abstract: A system including an encoder module, a buffer first-in first-out (FIFO) module, a buffer manager module, N FIFO modules, and N input/output (I/O) modules. The encoder module encodes data received from a host and generates P units of encoded data, where P is an integer greater than 1. The buffer FIFO module receives the P units from the encoder module and outputs the P units. The buffer manager module receives the P units from the buffer FIFO module, stores the P units in a buffer, retrieves N of the P units from the buffer, and outputs the N units in parallel, where N is an integer greater than 1. The N FIFO modules respectively receive the N units in parallel directly from the buffer manager. The N I/O modules receive the N units from the N FIFO modules in parallel, respectively, and output the N units to a storage medium.

Abstract: A data storage device includes a non-volatile semiconductor storage device and a controller that is configured to perform interleaving of small reads with large reads and small writes with large writes. In the example of reads, the controller receives a sequence of read commands including a first read command having a read size larger than a read threshold size and a second read command having a read size smaller than the read threshold size, and issue first and second read requests in succession to read data of a predetermined size less than the read threshold size, from the non-volatile semiconductor storage device. The interleaving is achieved by issuing the first read request to execute the first read command and the second read request to execute the second read command. As a result of this interleaving, the second read command will have a chance to complete earlier than the first read command even though it was received by the controller later in time.

Abstract: A cryptographic device includes first and second pipeline stages and a pipeline register. The first pipeline stage includes a first byte substitution module configured to (i) receive a first data block including multiple bytes, (ii) perform predetermined mathematical operations on each of the bytes of the first data block, and (iii) for each of the bytes of the first data block, output an intermediate value based on the predetermined mathematical operations. The pipeline register is configured to store the intermediate values. The second pipeline stage includes a second byte substitution module configured to (i) receive the stored intermediate values from the pipeline register, and (ii) generate an output data block, for each intermediate value of the stored intermediate values, by performing predetermined mathematical operations on the intermediate value to generate a corresponding replacement byte of the output data block.

Abstract: A storage drive includes a first memory that stores first text. A first processor generates a first instruction to decrypt the first text. A cryptographic module includes a second memory, a cryptographic device, a memory module, and a second processor. The second memory is inaccessible to the first processor and stores a cryptographic key. The cryptographic device accesses the second memory to obtain the cryptographic key and based on the first instruction, decrypts the first text. The memory module stores a status of execution of the first instruction by the cryptographic device. The second processor, prior to the cryptographic device decrypting the first text, forwards the first instruction to the cryptographic device and stores the status of execution of the first instruction in the memory module. The memory module is connected between the first and second processors and isolates the first processor from the second processor.

Abstract: A system including a non-volatile semiconductor memory (NVSM), an interface module and a control module. The NVSM stores first and second blocks of data. The first or second block of data is non-page based such that a size of the first block of data or a size of the second block of data is not an integer multiple of a page of data. The interface module transfers the first and second blocks of data during respectively a first data transfer event and a second data transfer event. The control module, based on descriptors, controls the first and second data transfer events such that the interface module transfers the first block of data between the interface module and the NVSM while transferring the second block of data between the interface module and the NVSM. The descriptors include respective sets of instructions for transferring the first and second blocks of data.

Abstract: An integrated circuit including a first interface, a decoder, and a controller. The first interface is configured to (i) write encoded data in a portion of a flash memory, and (ii) read the encoded data back from the flash memory. The decoder is configured to (i) according to an error correction code, decode the encoded data read back from the flash memory, and (ii) based on the decoded data, determine a number of decoding errors corresponding to the decoded data. The controller is configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the portion of the flash memory. The first threshold is less than a number of errors correctable by the error correction code for the portion of the flash memory.

Abstract: A hardware architecture for encryption and decryption device can improve the encryption and decryption data rate by using parallel processing, and pipeline operation, and save footprint by sharing hardware components. The hardware architecture can also be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit to encrypt a second portion of the array of data blocks, and a data block combiner to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks.

Abstract: A system including a non-volatile semiconductor memory (NVSM), an interface module and a control module. The NVSM stores first and second blocks of data. The first or second block of data is non-page based such that a size of the first block of data or a size of the second block of data is not an integer multiple of a page of data. The interface module transfers the first and second blocks of data during respectively a first data transfer event and a second data transfer event. The control module, based on descriptors, controls the first and second data transfer events such that the interface module transfers the first block of data between the interface module and the NVSM while transferring the second block of data between the interface module and the NVSM. The descriptors include respective sets of instructions for transferring the first and second blocks of data.

Abstract: Embodiments of the present disclosure provide apparatuses and methods for determining a compacting arrangement to store logical addressable units, which include compressed data sectors, into hardware addressable units of a storage device. The compacting arrangement is based on compression information associated with the logical addressable units. A write module is used to write the compressed data sectors to the storage device according to the compacting arrangement.

Abstract: A control system includes a control module configured to control data transfer events of blocks of data between an interface management module and a non-volatile semiconductor memory based on at least two descriptors for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive. A command management module is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event.

Abstract: A system including an encoder module, a buffer first-in first-out (FIFO) module, a buffer manager module, N FIFO modules, and N input/output (I/O) modules. The encoder module encodes data received from a host and generates P units of encoded data, where P is an integer greater than 1. The buffer FIFO module receives the P units from the encoder module and outputs the P units. The buffer manager module receives the P units from the buffer FIFO module, stores the P units in a buffer, retrieves N of the P units from the buffer, and outputs the N units in parallel, where N is an integer greater than 1. The N FIFO modules respectively receive the N units in parallel directly from the buffer manager. The N I/O modules receive the N units from the N FIFO modules in parallel, respectively, and output the N units to a storage medium.

Abstract: Methods, systems and computer program products for providing a sequencer that schedules job descriptors are described. The sequencer can manage the scheduling of the job descriptors for execution based on the availability of their respective segments and channels. For example, the sequencer can check the status of the segments, and identify one or more segments that are in busy or full state, or one or more segments that are in non-busy or empty state. Based on the status check, the sequencer can execute job descriptors out of order, and in particular, give priorities to job descriptors whose associated segments are available over job descriptors whose associated segments are in busy or full state.

Abstract: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

Abstract: A cryptographic device includes a first state module, a key addition module, a byte substitution module, and a column mixing module. The first state module stores a first data block. The key addition module adds a key to the first data block to generate a second data block. The byte substitution module replaces each byte of the second data block to generate a third data block. The byte substitution module includes a first byte substitution sub-module that generates an intermediate data block in response to the second data block, a pipeline register that stores the intermediate data block, and a second byte substitution sub-module that generates the third data block in response to the intermediate data block. The column mixing module generates a fourth data block based on the third data block and provides the fourth data block to the first state module for storage.

Abstract: A system includes a flash memory, an encoder, a first interface, a decoder and a controller. The encoder is configured to (i) receive data, and (ii) encode the data based on an error correction code. The first interface is configured to (i) write the encoded data to a memory cells in the flash memory, and (ii) read the encoded data back from the memory cells. The decoder is configured to (i) decode the encoded data read back from the memory cells, and (ii) based on the decoded data, determine a number of decoding errors for the plurality of memory cells. The controller is configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the memory cells. The first threshold is less than a maximum number of errors correctable by the error correction code for the memory cells.

Abstract: A hard disk controller (HDC) of a hard disk drive (HDD) includes an encoder module, a buffer manager module, N first-in first-out (FIFO) modules, and N read channel modules, where N is an integer greater than 1. The encoder module is configured to encode data received from a host and to generate P units of encoded data, where P is an integer greater than 1. The buffer manager module is configured to store the P units of encoded data in a buffer, retrieve N of the P units from the buffer, and output the N units in parallel. The N FIFO modules are configured to receive the N units in parallel from the buffer manager. The N read channel modules are configured to receive the N units from the N FIFO modules in parallel, respectively, and to output the N units to a magnetic medium of the HDD.

Abstract: The present disclosure includes systems and techniques relating to solid state drive controllers. In some implementations, a device includes a buffer that holds a block of data corresponding to a command from a host. The command identifies the block of data and a logical sequence in which the identified block of data is to be transmitted. In response to the command, a data retriever included in the device retrieves the portions of the block of data from non-volatile memory units in a retrieval sequence that is different from the logical sequence. When the device receives multiple commands identifying multiple blocks of data, the device services the commands in parallel by retrieving portions of blocks of data identified by both commands.

Abstract: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

Abstract: Apparatus having corresponding methods and computer-readable media comprise an encoder configured to provide encoded data according to an error correction code; a flash memory interface configured to write the encoded data to a location in flash memory, and to read the encoded data from the location in the flash memory; a decoder configured to decode the encoded data read from the location in the flash memory, and to indicate a number of resulting decode errors; and a retirement module configured to retire the location responsive to a number of resulting decode errors reaching an error threshold T.