Patents by Inventor Fred B. Jenne

Fred B. Jenne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4647956
    Abstract: A CMOS semiconductor device which avoids latchup in the powerup mode as well as in the normal operating mode is provided. The device is provided with an on-chip back bias generator which greatly reduces the possibility of forward biasing parasitic NPNP transistors in normal operation. During the powerup mode, before the backbias voltage becomes effective, a clamp diode provided in integrated form outside a guardring surrounding the circuit elements is effective to clamp a large negative voltage that may be created by a "hot-socket" connection to an output. In a modified form of the invention, a junction field effect transistor is provided to prevent forward biasing of the parasitic transistors in a somewhat different manner.
    Type: Grant
    Filed: February 12, 1985
    Date of Patent: March 3, 1987
    Assignee: Cypress Semiconductor Corp.
    Inventors: Rituparna Shrivastava, Raymond E. Bloker, Fred B. Jenne