Abstract: The inclusion of split power buses in standard cells enables the modification of IC performance through separate control over the width of the power bus and the size of active devices within the cell. This allows problems such as excessive voltage drop on power buses, insufficient power handling capability within the cell, excessive current consumption within the cell and so forth, to be corrected without major redesign of the cells or the IC.

Abstract: A large scale integrated semiconductor array consisting of a layout of predefined uncommitted active circuit components such as transistors which provide for logic function implementation and chip interfacing along with a region of passive circuit components used for signal and power routing. The various components are adapted to be interconnected on a single level which renders it particularly adaptable for automated layout techniques. The array is comprised of a plurality of rows of identical basic internal cells which are symmetrical and separated by an inner roadbed area consisting of at least three, but preferably five, vertical tunnel patterns, each of which is adapted to accommodate three horizontal wiring channels overhead for providing horizontal signal routing.