Abstract: A semiconductor manufacturing process for forming a three-dimensional (3D) memory structure and a semiconductor device having a 3D memory structure is described. The 3D memory structure comprises layers of memory cells with L shaped conductive layers where the L shaped conductive layers of each layer are coupled to metal lines disposed above the top or upper most layer such that the memory cells in each layer can be coupled to control circuitry.

Abstract: A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

Abstract: Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed that utilize NAND strings of serially-connected non-volatile memory cells. One such string can include two or more serially connected non-volatile memory cells each having a channel region. Each memory cell of the two or more serially connected non-volatile memory cells shares a common control gate and each memory cell of the two or more serially connected non-volatile memory cells is configured to receive an individual bias to its channel region.

Abstract: Semiconductor devices have conductive material lining a first opening in an insulative material and in contact with a metal silicide layer at the base of the opening overlying an active area within a silicon material and lining a second opening in the insulative material in direct contact with a polysilicon plug having substantially no metal silicide situated thereon.

Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM (dynamic random access memory) circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.

Abstract: Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed that utilize NAND strings of serially-connected non-volatile memory cells. One such string can include two or more serially connected non-volatile memory cells each having a channel region. Each memory cell of the two or more serially connected non-volatile memory cells shares a common control gate and each memory cell of the two or more serially connected non-volatile memory cells is configured to receive an individual bias to its channel region.

Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.

Abstract: Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed that utilize NAND strings of serially-connected non-volatile memory cells. One such string can include two or more serially connected non-volatile memory cells each having a channel region. Each memory cell of the two or more serially connected non-volatile memory cells shares a common control gate and each memory cell of the two or more serially connected non-volatile memory cells is configured to receive an individual bias to its channel region.

Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.

Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. In some embodiments, the method includes forming a metallized contact to an active area in a silicon substrate in a peripheral circuitry area and a metallized contact to a polysilicon plug in a memory cell array area by forming a first opening to expose the active area at the peripheral circuitry area, chemical vapor depositing a titanium layer over the dielectric layer and into the first opening to form a titanium silicide layer over the active area in the silicon substrate, removing the titanium layer selective to the titanium silicide layer, forming a second opening in the dielectric layer to expose the polysilicon plug at the memory cell array area, and forming metal contacts within the first and second openings to the active area and the exposed polysilicon plug.

Abstract: This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. In an alternate embodiment, a contact structure is fabricated by forming a polysilicon layer on a substrate, forming a tungsten nitride layer above the polysilicon layer, and etching the polysilicon layer and the tungsten nitride layer to a level below the surface of a substrate structure. A silicon nitride layer is formed above the tungsten nitride layer, and a ruthenium silicide layer is formed above the silicon nitride layer. The ruthenium silicide layer is then polished.

Abstract: Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high aspect ratio features in the underlying substrate. Some disclosed methods also enable simultaneous formation of hardmask structures of various dimensions, of both conventional and subresolution size, to enable etching structural features of different sizes in the underlying substrate.

Abstract: The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.

Abstract: The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.