Abstract: A method (and structure) of improving at least one of speed and efficiency when executing a linear algebra subroutine on a computer having a memory hierarchical structure including at least one cache, the computer having M levels of caches and a main memory. Based on sizes, it is determined, for a level 3 matrix multiplication processing, which matrix will have data for a submatrix block residing in a lower level cache of the computer and which two matrices will have data for submatrix blocks residing in at least one higher level cache or a memory. From a plurality of six kernels, two kernels are selected as optimal to use for executing the level 3 matrix multiplication processing as data streams from different levels of the M levels of cache, such that the processor will switch back and forth between the two selected kernels as streaming data traverses the different levels of cache.

Abstract: A method (and structure) of executing a matrix operation, includes, for a matrix A, separating the matrix A into blocks, each block having a size p-by-q. The blocks of size p-by-q are then stored in a cache or memory in at least one of the two following ways. The elements in at least one of the blocks is stored in a format in which elements of the block occupy a location different from an original location in the block, and/or the blocks of size p-by-q are stored in a format in which at least one block occupies a position different relative to its original position in the matrix A.

Abstract: A method (and structure) of executing a matrix operation, includes, for a matrix A, separating the matrix A into blocks, each block having a size p-by-q. The blocks of size p-by-q are then stored in a cache or memory in at least one of the two following ways. The elements in at least one of the blocks is stored in a format in which elements of the block occupy a location different from an original location in the block, and/or the blocks of size p-by-q are stored in a format in which at least one block occupies a position different relative to its original position in the matrix A.

Abstract: A signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform a method to at least one of reduce a memory space requirement and to increase a processing efficiency in a computerized method of linear algebra processing. A hybrid full-packed data structure is generated for processing data of a triangular matrix by one or more dense linear algebra (DLA) matrix subroutines designed to process matrix data in a full format, as modified to process matrix data using said hybrid full-packed data structure into a hybrid full-packed data structure, as follows. A portion of the triangular matrix data is determined that would comprise a square portion having a dimension approximately one half a dimension of the triangular matrix data.

Abstract: A method (and structure) of linear algebra processing, including processing a matrix data of a triangular packed format matrix in at least one matrix subroutine designed to process matrix data in a full format, using a hybrid full-packed data structure that provides a rectangular data structure for the triangular packed data.

Abstract: A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.

Abstract: A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations.

Abstract: An arithmetic unit keeps a result in carry-save form and uses this form of the result as an input to the next iteration in recurrent computations. The full adder in the recurrent path is eliminated by implementing multiplication by Y(i), where Y(i) is available only in carry-save form. The carry-save arithmetic unit generates a plurality of partial products whose sum is the product AXB, where A is one binary input and B is either a second binary input B' or the sum C'+S' of two binary inputs C' and S'. A selection is made as to whether B is equal to B' or C'+S'. The plurality of partial products and an addition input Z are compressed to two partial products C and S whose sum C+S equals the sum of the plurality of partial products and Z. The partial products C and S are added to produce a binary result X equal to A.times.B+Z. The full adder in the recurrent path is eliminated by a feedback path which returns the partial products C and S to the inputs C' and S' for a next iteration.